| Message ID | 20220629213508.1989600-3-martin.blumenstingl@googlemail.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | intel-nand-controller: Fixes, cleanups and questions | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 1 warnings, 8 lines checked |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Wed, 29 Jun 2022 23:35:02 +0200, Martin Blumenstingl wrote: > The Intel LGM NAND IP only supports two chip selects: There's only two > CS and ADDR_SEL register sets. Fix the maximum allowed chip select value > according to the dt-bindings. > > Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC") > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml index c45dd87fb5fd..af99b8f7c681 100644 --- a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml @@ -51,7 +51,7 @@ patternProperties: properties: reg: minimum: 0 - maximum: 7 + maximum: 1 nand-ecc-mode: true
The Intel LGM NAND IP only supports two chip selects: There's only two CS and ADDR_SEL register sets. Fix the maximum allowed chip select value according to the dt-bindings. Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)