diff mbox series

[v1,2/9] dt-bindings: reset: intel,rcu-gw: Allow up to three global reset items

Message ID 20220628124441.2385023-3-martin.blumenstingl@googlemail.com
State Not Applicable, archived
Headers show
Series reset: replace reset-lantiq with reset-intel-gw | expand

Checks

Context Check Description
robh/checkpatch warning total: 0 errors, 1 warnings, 15 lines checked
robh/patch-applied success
robh/dtbs-check warning build log
robh/dt-meta-schema success

Commit Message

Martin Blumenstingl June 28, 2022, 12:44 p.m. UTC
Legacy SoCs use three elements for the global reset:
- offset
- reset bit
- status bit

Allow this in the dt-bindings as well.

Fixes: b7ab0cb00d086b ("dt-bindings: reset: Add YAML schemas for the Intel Reset controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Rob Herring July 1, 2022, 4:26 p.m. UTC | #1
On Tue, 28 Jun 2022 14:44:34 +0200, Martin Blumenstingl wrote:
> Legacy SoCs use three elements for the global reset:
> - offset
> - reset bit
> - status bit
> 
> Allow this in the dt-bindings as well.
> 
> Fixes: b7ab0cb00d086b ("dt-bindings: reset: Add YAML schemas for the Intel Reset controller")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
index 13bf6bb3f097..be64f8597710 100644
--- a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
+++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
@@ -22,11 +22,15 @@  properties:
   intel,global-reset:
     description: Global reset register offset and bit offset.
     $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 2
     items:
       - description: Register offset
       - description: Register bit offset
         minimum: 0
         maximum: 31
+      - description: Status bit offset (only if "#reset-cells" is 3)
+        minimum: 0
+        maximum: 31
 
   "#reset-cells":
     minimum: 2