| Message ID | 20220626021148.56740-2-samuel@sholland.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | pinctrl: sunxi: Allwinner D1/D1s support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 26/06/2022 04:11, Samuel Holland wrote: > D1 contains a pin controller similar to previous SoCs, but with some > register layout changes. It includes 6 interrupt-capable pin banks. > > D1s is a low pin count version of the D1 SoC, with some pins omitted. > The remaining pins have the same function assignments as D1. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Am Sonntag, 26. Juni 2022, 04:11:42 CEST schrieb Samuel Holland: > D1 contains a pin controller similar to previous SoCs, but with some > register layout changes. It includes 6 interrupt-capable pin banks. > > D1s is a low pin count version of the D1 SoC, with some pins omitted. > The remaining pins have the same function assignments as D1. > > Signed-off-by: Samuel Holland <samuel@sholland.org> On a D1-Nezha Tested-by: Heiko Stuebner <heiko@sntech.de>
On Sun, Jun 26, 2022 at 4:11 AM Samuel Holland <samuel@sholland.org> wrote: > D1 contains a pin controller similar to previous SoCs, but with some > register layout changes. It includes 6 interrupt-capable pin banks. > > D1s is a low pin count version of the D1 SoC, with some pins omitted. > The remaining pins have the same function assignments as D1. > > Signed-off-by: Samuel Holland <samuel@sholland.org> All 6 patches applied to the pinctrl tree, the last patch 6/6 required some fuzzing so please check the result! Yours, Linus Walleij
Hi Linus, On 7/11/22 3:58 AM, Linus Walleij wrote: > On Sun, Jun 26, 2022 at 4:11 AM Samuel Holland <samuel@sholland.org> wrote: > >> D1 contains a pin controller similar to previous SoCs, but with some >> register layout changes. It includes 6 interrupt-capable pin banks. >> >> D1s is a low pin count version of the D1 SoC, with some pins omitted. >> The remaining pins have the same function assignments as D1. >> >> Signed-off-by: Samuel Holland <samuel@sholland.org> > > All 6 patches applied to the pinctrl tree, the last patch 6/6 > required some fuzzing so please check the result! Somehow the version of patch 6 applied to the pinctrl tree did not include the new driver source file. It only applied changes to existing files (including the Makefile reference to the new file). I also needed to make some minor changes to patch 6 to resolve comments from Andre. Is it okay if I send a v2 of just patch 6? Or do I need to send a follow-up based on what was already applied? Regards, Samuel
On 7/12/22 5:14 AM, Samuel Holland wrote: > Hi Linus, > > On 7/11/22 3:58 AM, Linus Walleij wrote: >> On Sun, Jun 26, 2022 at 4:11 AM Samuel Holland <samuel@sholland.org> wrote: >> >>> D1 contains a pin controller similar to previous SoCs, but with some >>> register layout changes. It includes 6 interrupt-capable pin banks. >>> >>> D1s is a low pin count version of the D1 SoC, with some pins omitted. >>> The remaining pins have the same function assignments as D1. >>> >>> Signed-off-by: Samuel Holland <samuel@sholland.org> >> >> All 6 patches applied to the pinctrl tree, the last patch 6/6 >> required some fuzzing so please check the result! I do not see anything in patch 6 that would have required a 3-way merge, so I don't understand what the issue was here. > Somehow the version of patch 6 applied to the pinctrl tree did not include the > new driver source file. It only applied changes to existing files (including the > Makefile reference to the new file). > > I also needed to make some minor changes to patch 6 to resolve comments from Andre. > > Is it okay if I send a v2 of just patch 6? Or do I need to send a follow-up > based on what was already applied? I sent a v2 of the whole series: https://lore.kernel.org/linux-gpio/20220713025233.27248-1-samuel@sholland.org/ Please let me know if you want something different. Regards, Samuel
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index bfce850c2035..3da52814f151 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -46,6 +46,8 @@ properties: - allwinner,sun8i-v3s-pinctrl - allwinner,sun9i-a80-pinctrl - allwinner,sun9i-a80-r-pinctrl + - allwinner,sun20i-d1-pinctrl + - allwinner,sun20i-d1s-pinctrl - allwinner,sun50i-a64-pinctrl - allwinner,sun50i-a64-r-pinctrl - allwinner,sun50i-a100-pinctrl @@ -171,6 +173,19 @@ allOf: minItems: 7 maxItems: 7 + - if: + properties: + compatible: + enum: + - allwinner,sun20i-d1-pinctrl + - allwinner,sun20i-d1s-pinctrl + + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + - if: properties: compatible:
D1 contains a pin controller similar to previous SoCs, but with some register layout changes. It includes 6 interrupt-capable pin banks. D1s is a low pin count version of the D1 SoC, with some pins omitted. The remaining pins have the same function assignments as D1. Signed-off-by: Samuel Holland <samuel@sholland.org> --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+)