| Message ID | 20220520030625.145324-1-chanho61.park@samsung.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | dt-bindings: clock: exynosautov9: correct count of NR_CLK | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 1 warnings, 55 lines checked |
| robh/patch-applied | fail | build log |
On 5/20/22 12:06 PM, Chanho Park wrote: > _NR_CLKS which can be used to register clocks via nr_clk_ids. The clock > IDs are started from 1. So, _NR_CLKS should be defined to "the last > clock id + 1" > > Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9") > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- > include/dt-bindings/clock/samsung,exynosautov9.h | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h > index 71ec0a955364..ea9f91b4eb1a 100644 > --- a/include/dt-bindings/clock/samsung,exynosautov9.h > +++ b/include/dt-bindings/clock/samsung,exynosautov9.h > @@ -166,7 +166,7 @@ > #define GOUT_CLKCMU_PERIC1_IP 248 > #define GOUT_CLKCMU_PERIS_BUS 249 > > -#define TOP_NR_CLK 249 > +#define TOP_NR_CLK 250 > > /* CMU_BUSMC */ > #define CLK_MOUT_BUSMC_BUS_USER 1 > @@ -174,7 +174,7 @@ > #define CLK_GOUT_BUSMC_PDMA0_PCLK 3 > #define CLK_GOUT_BUSMC_SPDMA_PCLK 4 > > -#define BUSMC_NR_CLK 4 > +#define BUSMC_NR_CLK 5 > > /* CMU_CORE */ > #define CLK_MOUT_CORE_BUS_USER 1 > @@ -183,7 +183,7 @@ > #define CLK_GOUT_CORE_CCI_PCLK 4 > #define CLK_GOUT_CORE_CMU_CORE_PCLK 5 > > -#define CORE_NR_CLK 5 > +#define CORE_NR_CLK 6 > > /* CMU_FSYS2 */ > #define CLK_MOUT_FSYS2_BUS_USER 1 > @@ -194,7 +194,7 @@ > #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6 > #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7 > > -#define FSYS2_NR_CLK 7 > +#define FSYS2_NR_CLK 8 > > /* CMU_PERIC0 */ > #define CLK_MOUT_PERIC0_BUS_USER 1 > @@ -240,7 +240,7 @@ > #define CLK_GOUT_PERIC0_PCLK_10 41 > #define CLK_GOUT_PERIC0_PCLK_11 42 > > -#define PERIC0_NR_CLK 42 > +#define PERIC0_NR_CLK 43 > > /* CMU_PERIC1 */ > #define CLK_MOUT_PERIC1_BUS_USER 1 > @@ -286,7 +286,7 @@ > #define CLK_GOUT_PERIC1_PCLK_10 41 > #define CLK_GOUT_PERIC1_PCLK_11 42 > > -#define PERIC1_NR_CLK 42 > +#define PERIC1_NR_CLK 43 > > /* CMU_PERIS */ > #define CLK_MOUT_PERIS_BUS_USER 1 > @@ -294,6 +294,6 @@ > #define CLK_GOUT_WDT_CLUSTER0 3 > #define CLK_GOUT_WDT_CLUSTER1 4 > > -#define PERIS_NR_CLK 4 > +#define PERIS_NR_CLK 5 > > #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */ > Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
On 20/05/2022 05:06, Chanho Park wrote: > _NR_CLKS which can be used to register clocks via nr_clk_ids. The clock > IDs are started from 1. So, _NR_CLKS should be defined to "the last > clock id + 1" > > Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9") > Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Quoting Chanho Park (2022-05-19 20:06:25) > _NR_CLKS which can be used to register clocks via nr_clk_ids. The clock > IDs are started from 1. So, _NR_CLKS should be defined to "the last > clock id + 1" > > Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9") > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- Applied to clk-next
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h index 71ec0a955364..ea9f91b4eb1a 100644 --- a/include/dt-bindings/clock/samsung,exynosautov9.h +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -166,7 +166,7 @@ #define GOUT_CLKCMU_PERIC1_IP 248 #define GOUT_CLKCMU_PERIS_BUS 249 -#define TOP_NR_CLK 249 +#define TOP_NR_CLK 250 /* CMU_BUSMC */ #define CLK_MOUT_BUSMC_BUS_USER 1 @@ -174,7 +174,7 @@ #define CLK_GOUT_BUSMC_PDMA0_PCLK 3 #define CLK_GOUT_BUSMC_SPDMA_PCLK 4 -#define BUSMC_NR_CLK 4 +#define BUSMC_NR_CLK 5 /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 @@ -183,7 +183,7 @@ #define CLK_GOUT_CORE_CCI_PCLK 4 #define CLK_GOUT_CORE_CMU_CORE_PCLK 5 -#define CORE_NR_CLK 5 +#define CORE_NR_CLK 6 /* CMU_FSYS2 */ #define CLK_MOUT_FSYS2_BUS_USER 1 @@ -194,7 +194,7 @@ #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6 #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7 -#define FSYS2_NR_CLK 7 +#define FSYS2_NR_CLK 8 /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_BUS_USER 1 @@ -240,7 +240,7 @@ #define CLK_GOUT_PERIC0_PCLK_10 41 #define CLK_GOUT_PERIC0_PCLK_11 42 -#define PERIC0_NR_CLK 42 +#define PERIC0_NR_CLK 43 /* CMU_PERIC1 */ #define CLK_MOUT_PERIC1_BUS_USER 1 @@ -286,7 +286,7 @@ #define CLK_GOUT_PERIC1_PCLK_10 41 #define CLK_GOUT_PERIC1_PCLK_11 42 -#define PERIC1_NR_CLK 42 +#define PERIC1_NR_CLK 43 /* CMU_PERIS */ #define CLK_MOUT_PERIS_BUS_USER 1 @@ -294,6 +294,6 @@ #define CLK_GOUT_WDT_CLUSTER0 3 #define CLK_GOUT_WDT_CLUSTER1 4 -#define PERIS_NR_CLK 4 +#define PERIS_NR_CLK 5 #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */
_NR_CLKS which can be used to register clocks via nr_clk_ids. The clock IDs are started from 1. So, _NR_CLKS should be defined to "the last clock id + 1" Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9") Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- include/dt-bindings/clock/samsung,exynosautov9.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)