| Message ID | 20220517073518.34474-2-peng.fan@oss.nxp.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | mailbox: imx: support RST channel | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Tue, 17 May 2022 15:35:17 +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > i.MX MU has a MUR bit which is to reset both the Processor B and the > Processor A sides of the MU module, forcing all control and status > registers to return to their default values (except the BHR bit in the ACR > register and BHRM bit in BCR register), and all internal states to be > cleared. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml index 7a86e7926dd2..191c1ce15009 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml @@ -72,14 +72,16 @@ properties: type : Channel type channel : Channel number - This MU support 4 type of unidirectional channels, each type - has 4 channels. A total of 16 channels. Following types are + This MU support 5 type of unidirectional channels, each type + has 4 channels except RST channel which only has 1 channel. + A total of 17 channels. Following types are supported: 0 - TX channel with 32bit transmit register and IRQ transmit acknowledgment support. 1 - RX channel with 32bit receive register and IRQ support 2 - TX doorbell channel. Without own register and no ACK support. 3 - RX doorbell channel. + 4 - RST channel const: 2 clocks: