| Message ID | 20220513165050.500831-5-angelogioacchino.delregno@collabora.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | MediaTek Helio X10 MT6795 - Clock drivers | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dt-meta-schema | fail | build log |
On Fri, 13 May 2022 18:50:49 +0200, AngeloGioacchino Del Regno wrote: > Add the bindings for the clock drivers of the MediaTek Helio X10 > MT6795 SoC. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../arm/mediatek/mediatek,mt6795-clock.yaml | 67 +++++++++++++++++ > .../mediatek/mediatek,mt6795-sys-clock.yaml | 73 +++++++++++++++++++ > 2 files changed, 140 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml:67:1: [warning] too many blank lines (2 > 1) (empty-lines) dtschema/dtc warnings/errors: Error: Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.example.dts:35.13-21 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1401: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Fri, May 13, 2022 at 06:50:49PM +0200, AngeloGioacchino Del Regno wrote: > Add the bindings for the clock drivers of the MediaTek Helio X10 > MT6795 SoC. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../arm/mediatek/mediatek,mt6795-clock.yaml | 67 +++++++++++++++++ > .../mediatek/mediatek,mt6795-sys-clock.yaml | 73 +++++++++++++++++++ > 2 files changed, 140 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml > new file mode 100644 > index 000000000000..b7d96d0ed867 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MediaTek Functional Clock Controller for MT6795 > + > +maintainers: > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + - Chun-Jie Chen <chun-jie.chen@mediatek.com> > + > +description: | > + The clock architecture in MediaTek like below > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The devices provide clock gate control in different IP blocks. > + > +properties: > + compatible: > + items: Don't need 'items' if only 1 item. > + - enum: > + - mediatek,mt6795-mfgcfg > + - mediatek,mt6795-vdecsys > + - mediatek,mt6795-vencsys blank line. > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg Why is #clock-cells optional? > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + clock-controller@13000000 { > + compatible = "mediatek,mt6795-mfgcfg"; > + reg = <0 0x13000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + clock-controller@16000000 { > + compatible = "mediatek,mt6795-vdecsys"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + clock-controller@18000000 { > + compatible = "mediatek,mt6795-vdecsys"; > + reg = <0 0x18000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > + > + > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml > new file mode 100644 > index 000000000000..389dd8e245ac > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-sys-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MediaTek System Clock Controller for MT6795 > + > +maintainers: > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + - Chun-Jie Chen <chun-jie.chen@mediatek.com> > + > +description: > + The Mediatek system clock controller provides various clocks and system configuration > + like reset and bus protection on MT6795. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt6795-apmixedsys > + - mediatek,mt6795-infracfg > + - mediatek,mt6795-pericfg > + - mediatek,mt6795-topckgen > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg #clock-cells? > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + topckgen: clock-controller@10000000 { > + compatible = "mediatek,mt6795-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: power-controller@10001000 { > + compatible = "mediatek,mt6795-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + } > + > + pericfg: power-controller@10003000 { > + compatible = "mediatek,mt6795-pericfg", "syscon"; > + reg = <0 0x10003000 0 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + apmixedsys: clock-controller@10209000 { > + compatible = "mediatek,mt6795-apmixedsys", "syscon"; > + reg = <0 0x10209000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > -- > 2.35.1 > >
Il 16/05/22 19:28, Rob Herring ha scritto: > On Fri, May 13, 2022 at 06:50:49PM +0200, AngeloGioacchino Del Regno wrote: >> Add the bindings for the clock drivers of the MediaTek Helio X10 >> MT6795 SoC. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> .../arm/mediatek/mediatek,mt6795-clock.yaml | 67 +++++++++++++++++ >> .../mediatek/mediatek,mt6795-sys-clock.yaml | 73 +++++++++++++++++++ >> 2 files changed, 140 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml >> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml >> >> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml >> new file mode 100644 >> index 000000000000..b7d96d0ed867 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml >> @@ -0,0 +1,67 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-clock.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: MediaTek Functional Clock Controller for MT6795 >> + >> +maintainers: >> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> + - Chun-Jie Chen <chun-jie.chen@mediatek.com> >> + >> +description: | >> + The clock architecture in MediaTek like below >> + PLLs --> >> + dividers --> >> + muxes >> + --> >> + clock gate >> + >> + The devices provide clock gate control in different IP blocks. >> + >> +properties: >> + compatible: >> + items: > > Don't need 'items' if only 1 item. > >> + - enum: >> + - mediatek,mt6795-mfgcfg >> + - mediatek,mt6795-vdecsys >> + - mediatek,mt6795-vencsys > > blank line. > >> + reg: >> + maxItems: 1 >> + >> + '#clock-cells': >> + const: 1 >> + >> +required: >> + - compatible >> + - reg > > Why is #clock-cells optional? > I've used one of the other mediatek,mt(something)-(sys-)clock.yaml as a base for these ones, giving for granted that they were correct, but now that you're pointing that out... effectively, I should've checked if the ones that are already merged in were correct *before* using these as a base for mine. Thanks for your review: I'll send a v2 soon... and I will also separately send some fixes for the existing ones, as your review comments also apply to these ones. Regards, Angelo
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml new file mode 100644 index 000000000000..b7d96d0ed867 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-clock.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Functional Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt6795-mfgcfg + - mediatek,mt6795-vdecsys + - mediatek,mt6795-vencsys + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@13000000 { + compatible = "mediatek,mt6795-mfgcfg"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@16000000 { + compatible = "mediatek,mt6795-vdecsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@18000000 { + compatible = "mediatek,mt6795-vdecsys"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; + }; + + diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml new file mode 100644 index 000000000000..389dd8e245ac --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-sys-clock.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek System Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: + The Mediatek system clock controller provides various clocks and system configuration + like reset and bus protection on MT6795. + +properties: + compatible: + items: + - enum: + - mediatek,mt6795-apmixedsys + - mediatek,mt6795-infracfg + - mediatek,mt6795-pericfg + - mediatek,mt6795-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6795-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: power-controller@10001000 { + compatible = "mediatek,mt6795-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + } + + pericfg: power-controller@10003000 { + compatible = "mediatek,mt6795-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt6795-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + };
Add the bindings for the clock drivers of the MediaTek Helio X10 MT6795 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../arm/mediatek/mediatek,mt6795-clock.yaml | 67 +++++++++++++++++ .../mediatek/mediatek,mt6795-sys-clock.yaml | 73 +++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml