| Message ID | 20220124201231.298961-4-maz@kernel.org |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | drivers/perf: CPU PMU driver for Apple M1 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dtbs-check | success | |
| robh/dt-meta-schema | success |
On Mon, Jan 24, 2022 at 08:12:24PM +0000, Marc Zyngier wrote: > Some of the FIQ per-cpu pseudo-interrupts are better described with > a specific affinity, the most obvious candidate being the CPU PMUs. > > Augment the AIC binding to be able to specify that affinity in the > interrupt controller node. > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > .../interrupt-controller/apple,aic.yaml | 27 +++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > index c7577d401786..d97683eb2c54 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > @@ -70,6 +70,33 @@ properties: > power-domains: > maxItems: 1 > > + affinities: > + type: object additionalProperties: false > + description: > + FIQ affinity can be expressed as a single "affinities" node, > + containing a set of sub-nodes, one per FIQ with a non-default > + affinity. > + patternProperties: > + "^.+-affinity$": > + type: object additionalProperties: false > + properties: > + fiq-index: apple,fiq-index With that, Reviewed-by: Rob Herring <robh@kernel.org> > + description: > + The interrupt number specified as a FIQ, and for which > + the affinity is not the default. > + $ref: /schemas/types.yaml#/definitions/uint32 > + maximum: 5 > + > + cpus: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Should be a list of phandles to CPU nodes (as described in > + Documentation/devicetree/bindings/arm/cpus.yaml). > + > + required: > + - fiq-index > + - cpus > + > required: > - compatible > - '#interrupt-cells' > -- > 2.30.2 > >
diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index c7577d401786..d97683eb2c54 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -70,6 +70,33 @@ properties: power-domains: maxItems: 1 + affinities: + type: object + description: + FIQ affinity can be expressed as a single "affinities" node, + containing a set of sub-nodes, one per FIQ with a non-default + affinity. + patternProperties: + "^.+-affinity$": + type: object + properties: + fiq-index: + description: + The interrupt number specified as a FIQ, and for which + the affinity is not the default. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - fiq-index + - cpus + required: - compatible - '#interrupt-cells'
Some of the FIQ per-cpu pseudo-interrupts are better described with a specific affinity, the most obvious candidate being the CPU PMUs. Augment the AIC binding to be able to specify that affinity in the interrupt controller node. Signed-off-by: Marc Zyngier <maz@kernel.org> --- .../interrupt-controller/apple,aic.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+)