From patchwork Thu Dec 16 05:53:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 1568902 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JF1Wj1zTqz9sCD for ; Thu, 16 Dec 2021 16:53:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231817AbhLPFxv (ORCPT ); Thu, 16 Dec 2021 00:53:51 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:53150 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231682AbhLPFxm (ORCPT ); Thu, 16 Dec 2021 00:53:42 -0500 X-UUID: 76fa4987f77848d68c39d489cd265db8-20211216 X-UUID: 76fa4987f77848d68c39d489cd265db8-20211216 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1177963592; Thu, 16 Dec 2021 13:53:39 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 16 Dec 2021 13:53:37 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 13:53:36 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , , , Subject: [PATCH net-next v10 6/6] net: dt-bindings: dwmac: add support for mt8195 Date: Thu, 16 Dec 2021 13:53:28 +0800 Message-ID: <20211216055328.15953-7-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216055328.15953-1-biao.huang@mediatek.com> References: <20211216055328.15953-1-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding document for the ethernet on mt8195. Signed-off-by: Biao Huang --- .../bindings/net/mediatek-dwmac.yaml | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml index 8ad6e19661b8..a12f822a9ded 100644 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml @@ -19,6 +19,7 @@ select: contains: enum: - mediatek,mt2712-gmac + - mediatek,mt8195-gmac required: - compatible @@ -27,26 +28,36 @@ allOf: properties: compatible: - items: - - enum: - - mediatek,mt2712-gmac - - const: snps,dwmac-4.20a + oneOf: + - items: + - enum: + - mediatek,mt2712-gmac + - const: snps,dwmac-4.20a + - items: + - enum: + - mediatek,mt8195-gmac + - const: snps,dwmac-5.10a clocks: + minItems: 5 items: - description: AXI clock - description: APB clock - description: MAC Main clock - description: PTP clock - description: RMII reference clock provided by MAC + - description: MAC clock gate clock-names: + minItems: 5 + maxItems: 6 items: - const: axi - const: apb - const: mac_main - const: ptp_ref - const: rmii_internal + - const: mac_cg mediatek,pericfg: $ref: /schemas/types.yaml#/definitions/phandle @@ -61,6 +72,8 @@ properties: or will round down. Range 0~31*170. For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, or will round down. Range 0~31*550. + For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290, + or will round down. Range 0~31*290. mediatek,rx-delay-ps: description: @@ -69,6 +82,8 @@ properties: or will round down. Range 0~31*170. For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, or will round down. Range 0~31*550. + For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple + of 290, or will round down. Range 0~31*290. mediatek,rmii-rxc: type: boolean @@ -102,6 +117,12 @@ properties: 3. the inside clock, which be sent to MAC, will be inversed in RMII case when the reference clock is from MAC. + mediatek,mac-wol: + type: boolean + description: + If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled. + Otherwise, PHY WOL is perferred. + required: - compatible - reg