| Message ID | 20211214182634.727330-4-maz@kernel.org |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | drivers/perf: CPU PMU driver for Apple M1 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dtbs-check | success | |
| robh/dt-meta-schema | success |
On Tue, Dec 14, 2021 at 06:26:27PM +0000, Marc Zyngier wrote: > Some of the FIQ per-cpu pseudo-interrupts are better described with > a specific affinity, the most obvious candidate being the CPU PMUs. > > Augment the AIC binding to be able to specify that affinity in the > interrupt controller node. > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > .../interrupt-controller/apple,aic.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > index b95e41816953..ac1c82cffa0a 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > @@ -67,6 +67,32 @@ properties: > Specifies base physical address and size of the AIC registers. > maxItems: 1 > > + affinities: > + type: object > + description: > + FIQ affinity can be expressed as a single "affinities" node, > + containing a set of sub-nodes, one per FIQ with a non-default > + affinity. > + patternProperties: > + "^.+-affinity$": > + type: object > + properties: > + fiq-index: > + description: > + The interrupt number specified as a FIQ, and for which > + the affinity is not the default. > + $ref: /schemas/types.yaml#/definitions/uint32 > + maximum: 5 blank line between each prop. > + affinity: 'cpus' is already somewhat established for list of phandles to cpu nodes. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Should be a list of phandles to CPU nodes (as described in > + Documentation/devicetree/bindings/arm/cpus.yaml). > + > + required: > + - fiq-index > + - affinity > + > required: > - compatible > - '#interrupt-cells' > -- > 2.30.2 > >
diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index b95e41816953..ac1c82cffa0a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -67,6 +67,32 @@ properties: Specifies base physical address and size of the AIC registers. maxItems: 1 + affinities: + type: object + description: + FIQ affinity can be expressed as a single "affinities" node, + containing a set of sub-nodes, one per FIQ with a non-default + affinity. + patternProperties: + "^.+-affinity$": + type: object + properties: + fiq-index: + description: + The interrupt number specified as a FIQ, and for which + the affinity is not the default. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + affinity: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - fiq-index + - affinity + required: - compatible - '#interrupt-cells'
Some of the FIQ per-cpu pseudo-interrupts are better described with a specific affinity, the most obvious candidate being the CPU PMUs. Augment the AIC binding to be able to specify that affinity in the interrupt controller node. Signed-off-by: Marc Zyngier <maz@kernel.org> --- .../interrupt-controller/apple,aic.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)