| Message ID | 20211007123632.697666-6-anup.patel@wdc.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Linux RISC-V ACLINT Support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | fail | build log |
On Thu, 07 Oct 2021 18:06:27 +0530, Anup Patel wrote: > We add DT bindings documentation for the ACLINT MSWI and SSWI > devices found on RISC-V SOCs. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > --- > .../riscv,aclint-swi.yaml | 97 +++++++++++++++++++ > 1 file changed, 97 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml:34:13: [warning] wrong indentation: expected 14 but found 12 (indentation) ./Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml:39:13: [warning] wrong indentation: expected 14 but found 12 (indentation) dtschema/dtc warnings/errors: doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1537678 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Fri, Oct 8, 2021 at 8:16 AM Rob Herring <robh@kernel.org> wrote: > > On Thu, 07 Oct 2021 18:06:27 +0530, Anup Patel wrote: > > We add DT bindings documentation for the ACLINT MSWI and SSWI > > devices found on RISC-V SOCs. > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > --- > > .../riscv,aclint-swi.yaml | 97 +++++++++++++++++++ > > 1 file changed, 97 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > ./Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml:34:13: [warning] wrong indentation: expected 14 but found 12 (indentation) > ./Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml:39:13: [warning] wrong indentation: expected 14 but found 12 (indentation) > > dtschema/dtc warnings/errors: > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/patch/1537678 > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: Ahh, I did not have "yamllint" installed. I am able to reproduce this warning with "yamllint". This will be fixed in v5. Let me know if you have any other comments apart from this. Regards, Anup > > pip3 install dtschema --upgrade > > Please check and re-submit. >
Hi all,
We are working on devicetree generation for rocket-chip, specifically
generating ACLINT nodes instead of CLINT nodes. (WIP at [1].) We were
wondering if riscv,aclint-{m,s}swi should really be an interrupt-controller.
According to the devicetree specification (v0.3 found at [2]), an
interrupt-controller *receives* interrupts. The ACLINT devices only ever
generates interrupts, so they would be classified as interrupt
generating device rather than interrupt controller or interrupt nexus.
These bindings, as is, require the MSWI and SSWI devices to have the
interrupt-controller property and #interrupt-cells = <0>, which does not
reflect its functionality. It nonsensically implies that another device
may have an interrupt routed through an MSWI/SSWI as interrupt-parent.
Removing these requirements makes more sense.
I'm not sure about what other node name to use though. It seems that
these are more like mailboxes, but also not exactly. In any case a
clarification of the bindings would be appreciated.
Thanks,
dram
[1]: https://github.com/chipsalliance/rocket-chip/pull/3330
[2]: https://www.devicetree.org/specifications/
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml new file mode 100644 index 000000000000..f034c18f46bd --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V ACLINT Software Interrupt Devices + +maintainers: + - Anup Patel <anup.patel@wdc.com> + +description: + RISC-V SOCs include an implementation of the M-level software interrupt + (MSWI) device and the S-level software interrupt (SSWI) device defined + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. + + The ACLINT MSWI and SSWI devices are documented in the RISC-V ACLINT + specification located at + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. + + The ACLINT MSWI and SSWI devices directly connect to the M-level and + S-level software interrupt lines of various HARTs (or CPUs) respectively + so the RISC-V per-HART (or per-CPU) local interrupt controller is the + parent interrupt controller for the ACLINT MSWI and SSWI devices. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - sifive,fu540-c000-aclint-mswi + - const: riscv,aclint-mswi + + - items: + - enum: + - vendor,chip-aclint-sswi + - const: riscv,aclint-sswi + + description: + For ACLINT MSWI devices, it should be "<vendor>,<chip>-aclint-mswi" + and "riscv,aclint-mswi". + For ACLINT SSWI devices, it should be "<vendor>,<chip>-aclint-sswi" + and "riscv,aclint-sswi". + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 0 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + + interrupt-controller: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + - interrupt-controller + - "#interrupt-cells" + +examples: + - | + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel): + + interrupt-controller@2000000 { + compatible = "sifive,fu540-c000-aclint-mswi", "riscv,aclint-mswi"; + interrupts-extended = <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + reg = <0x2000000 0x4000>; + interrupt-controller; + #interrupt-cells = <0>; + }; + + - | + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel): + + interrupt-controller@2f00000 { + compatible = "vendor,chip-aclint-sswi", "riscv,aclint-sswi"; + interrupts-extended = <&cpu1intc 1>, + <&cpu2intc 1>, + <&cpu3intc 1>, + <&cpu4intc 1>; + reg = <0x2f00000 0x4000>; + interrupt-controller; + #interrupt-cells = <0>; + }; +...