| Message ID | 20210828131814.29589-1-konrad.dybcio@somainline.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [v2,01/18] dt-bindings: arm: cpus: Add Kryo 560 CPUs | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 1 warnings, 7 lines checked |
| robh/dt-meta-schema | success | |
| robh/dtbs-check | fail | build log |
Hi, On 8/28/2021 6:48 PM, Konrad Dybcio wrote: > Add TLMM pinctrl node to enable referencing the SoC pins in other nodes. > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > Changes since v1: > - Fix the gpio ranges from 156 to 157 > > arch/arm64/boot/dts/qcom/sm6350.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index d57c669ae0d6..03f7601457b4 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -406,6 +406,25 @@ pdc: interrupt-controller@b220000 { > interrupt-controller; > }; > > + tlmm: pinctrl@f100000 { > + compatible = "qcom,sm6350-tlmm"; > + reg = <0 0x0f100000 0 0x300000>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; you will not require other interrupts (209 to 216) for dual edge to work since you have below set in pinctrl-sm6350.c .wakeirq_dual_edge_errata = true, Thanks, Maulik > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 157>; > + }; > + > intc: interrupt-controller@17a00000 { > compatible = "arm,gic-v3"; > #interrupt-cells = <3>;
On 28.08.2021 17:47, Maulik Shah wrote: > Hi, > > On 8/28/2021 6:48 PM, Konrad Dybcio wrote: >> Add TLMM pinctrl node to enable referencing the SoC pins in other nodes. >> >> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> --- >> Changes since v1: >> - Fix the gpio ranges from 156 to 157 >> >> arch/arm64/boot/dts/qcom/sm6350.dtsi | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi >> index d57c669ae0d6..03f7601457b4 100644 >> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >> @@ -406,6 +406,25 @@ pdc: interrupt-controller@b220000 { >> interrupt-controller; >> }; >> + tlmm: pinctrl@f100000 { >> + compatible = "qcom,sm6350-tlmm"; >> + reg = <0 0x0f100000 0 0x300000>; >> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; > you will not require other interrupts (209 to 216) for dual edge to work since you have below set in pinctrl-sm6350.c > > .wakeirq_dual_edge_errata = true, > > Thanks, > Maulik Right, I updated the binding but not the dt... Thanks for spotting that. Konrad
Hi, On 8/28/2021 6:47 PM, Konrad Dybcio wrote: > Add a base DT for SM6350 SoC > > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 487 +++++++++++++++++++++++++++ > 1 file changed, 487 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm6350.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > new file mode 100644 > index 000000000000..9a9797f5a55b > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -0,0 +1,487 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/mailbox/qcom-ipcc.h> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h> > + > +/ { > + interrupt-parent = <&intc>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <76800000>; > + clock-output-names = "xo_board"; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + clock-frequency = <32764>; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,kryo560"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + next-level-cache = <&L2_0>; > + #cooling-cells = <2>; > + L2_0: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + L3_0: l3-cache { > + compatible = "cache"; > + }; > + }; > + }; > + > + CPU1: cpu@100 { > + device_type = "cpu"; > + compatible = "qcom,kryo560"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + next-level-cache = <&L2_100>; > + #cooling-cells = <2>; > + L2_100: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU2: cpu@200 { > + device_type = "cpu"; > + compatible = "qcom,kryo560"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + next-level-cache = <&L2_200>; > + #cooling-cells = <2>; > + L2_200: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU3: cpu@300 { > + device_type = "cpu"; > + compatible = "qcom,kryo560"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + next-level-cache = <&L2_300>; > + #cooling-cells = <2>; > + L2_300: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU4: cpu@400 { > + device_type = "cpu"; > + compatible = "qcom,kryo560"; > + reg = <0x0 0x400>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + next-level-cache = <&L2_400>; > + #cooling-cells = <2>; > + L2_400: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU5: cpu@500 { > + device_type = "cpu"; > + compatible = "qcom,kryo560"; > + reg = <0x0 0x500>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + next-level-cache = <&L2_500>; > + #cooling-cells = <2>; > + L2_500: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + > + }; > + > + CPU6: cpu@600 { > + device_type = "cpu"; > + compatible = "qcom,kryo560"; > + reg = <0x0 0x600>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1894>; > + dynamic-power-coefficient = <703>; > + next-level-cache = <&L2_600>; > + #cooling-cells = <2>; > + L2_600: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU7: cpu@700 { > + device_type = "cpu"; > + compatible = "qcom,kryo560"; > + reg = <0x0 0x700>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1894>; > + dynamic-power-coefficient = <703>; > + next-level-cache = <&L2_700>; > + #cooling-cells = <2>; > + L2_700: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + > + core4 { > + cpu = <&CPU4>; > + }; > + > + core5 { > + cpu = <&CPU5>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&CPU6>; > + }; > + > + core1 { > + cpu = <&CPU7>; > + }; > + }; > + }; > + }; > + > + firmware { > + scm: scm { > + compatible = "qcom,scm-sm6350", "qcom,scm"; > + #reset-cells = <1>; > + }; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0x0 0x80000000 0x0 0x0>; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + hyp_mem: memory@80000000 { > + reg = <0 0x80000000 0 0x600000>; > + no-map; > + }; > + > + xbl_aop_mem: memory@80700000 { > + reg = <0 0x80700000 0 0x160000>; > + no-map; > + }; > + > + cmd_db: memory@80860000 { > + compatible = "qcom,cmd-db"; > + reg = <0 0x80860000 0 0x20000>; > + no-map; > + }; > + > + sec_apps_mem: memory@808ff000 { > + reg = <0 0x808ff000 0 0x1000>; > + no-map; > + }; > + > + smem_mem: memory@80900000 { > + reg = <0 0x80900000 0 0x200000>; > + no-map; > + }; > + > + cdsp_sec_mem: memory@80b00000 { > + reg = <0 0x80b00000 0 0x1e00000>; > + no-map; > + }; > + > + pil_camera_mem: memory@86000000 { > + reg = <0 0x86000000 0 0x500000>; > + no-map; > + }; > + > + pil_npu_mem: memory@86500000 { > + reg = <0 0x86500000 0 0x500000>; > + no-map; > + }; > + > + pil_video_mem: memory@86a00000 { > + reg = <0 0x86a00000 0 0x500000>; > + no-map; > + }; > + > + pil_cdsp_mem: memory@86f00000 { > + reg = <0 0x86f00000 0 0x1e00000>; > + no-map; > + }; > + > + pil_adsp_mem: memory@88d00000 { > + reg = <0 0x88d00000 0 0x2800000>; > + no-map; > + }; > + > + wlan_fw_mem: memory@8b500000 { > + reg = <0 0x8b500000 0 0x200000>; > + no-map; > + }; > + > + pil_ipa_fw_mem: memory@8b700000 { > + reg = <0 0x8b700000 0 0x10000>; > + no-map; > + }; > + > + pil_ipa_gsi_mem: memory@8b710000 { > + reg = <0 0x8b710000 0 0x5400>; > + no-map; > + }; > + > + pil_gpu_mem: memory@8b715400 { > + reg = <0 0x8b715400 0 0x2000>; > + no-map; > + }; > + > + pil_modem_mem: memory@8b800000 { > + reg = <0 0x8b800000 0 0xf800000>; > + no-map; > + }; > + > + cont_splash_memory: memory@a0000000 { > + reg = <0 0xa0000000 0 0x2300000>; > + no-map; > + }; > + > + dfps_data_memory: memory@a2300000 { > + reg = <0 0xa2300000 0 0x100000>; > + no-map; > + }; > + > + removed_region: memory@c0000000 { > + reg = <0 0xc0000000 0 0x3900000>; > + no-map; > + }; > + > + debug_region: memory@ffb00000 { > + reg = <0 0xffb00000 0 0xc0000>; > + no-map; > + }; > + > + last_log_region: memory@ffbc0000 { > + reg = <0 0xffbc0000 0 0x40000>; > + no-map; > + }; > + > + ramoops: ramoops@ffc00000 { > + compatible = "removed-dma-pool", "ramoops"; > + reg = <0 0xffc00000 0 0x00100000>; > + record-size = <0x1000>; > + console-size = <0x40000>; > + ftrace-size = <0x0>; > + msg-size = <0x20000 0x20000>; > + cc-size = <0x0>; > + no-map; > + }; > + > + cmdline_region: memory@ffd00000 { > + reg = <0 0xffd00000 0 0x1000>; > + no-map; > + }; > + }; > + > + smem { > + compatible = "qcom,smem"; > + memory-region = <&smem_mem>; > + hwlocks = <&tcsr_mutex 3>; > + }; > + > + soc: soc@0 { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + compatible = "simple-bus"; > + > + ipcc: mailbox@408000 { > + compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; > + reg = <0 0x00408000 0 0x1000>; > + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <3>; > + #mbox-cells = <2>; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x01f40000 0x0 0x40000>; > + #hwlock-cells = <1>; > + }; > + > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,sm6350-pdc", "qcom,pdc"; > + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; The second reg 0x17c000f0 is neither documented nor used in PDC irq chip driver. can you please remove it? Thanks, Maulik > + qcom,pdc-ranges = <0 480 94>, <94 609 31>, > + <125 63 1>, <126 655 12>, <138 139 15>; > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > + intc: interrupt-controller@17a00000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ > + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ > + interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + watchdog@17c10000 { > + compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; > + reg = <0 0x17c10000 0 0x1000>; > + clocks = <&sleep_clk>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + timer@17c20000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x0 0x17c20000 0x0 0x1000>; > + clock-frequency = <19200000>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + frame@17c21000 { > + frame-number = <0>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17c21000 0x0 0x1000>, > + <0x0 0x17c22000 0x0 0x1000>; > + }; > + > + frame@17c23000 { > + frame-number = <1>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17c23000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c25000 { > + frame-number = <2>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17c25000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c27000 { > + frame-number = <3>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17c27000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c29000 { > + frame-number = <4>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17c29000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c2b000 { > + frame-number = <5>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17c2b000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c2d000 { > + frame-number = <6>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17c2d000 0x0 0x1000>; > + status = "disabled"; > + }; > + }; > + > + apps_rsc: rsc@18200000 { > + compatible = "qcom,rpmh-rsc"; > + label = "apps_rsc"; > + reg = <0x0 0x18200000 0x0 0x10000>, > + <0x0 0x18210000 0x0 0x10000>, > + <0x0 0x18220000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, > + <WAKE_TCS 3>, <CONTROL_TCS 1>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + clock-frequency = <19200000>; > + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + }; > +};
>> + >> + tcsr_mutex: hwlock@1f40000 { >> + compatible = "qcom,tcsr-mutex"; >> + reg = <0x0 0x01f40000 0x0 0x40000>; >> + #hwlock-cells = <1>; >> + }; >> + >> + pdc: interrupt-controller@b220000 { >> + compatible = "qcom,sm6350-pdc", "qcom,pdc"; >> + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; > > The second reg 0x17c000f0 is neither documented nor used in PDC irq chip driver. can you please remove it? > > Thanks, > Maulik > Wouldn't it make more sense to keep it (like in other PDC-enabled SoCs' device trees) so that there's no need to add it back when the driver gains support for spi_configure_type (I believe that's what it's used for)? Konrad
Hi, On 8/28/2021 6:48 PM, Konrad Dybcio wrote: > Add a node for AOSS_QMP in preparation for remote processor enablement. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index 986d7fb01cbb..d903173b7dbc 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -537,6 +537,17 @@ tsens1: thermal-sensor@c265000 { > #thermal-sensor-cells = <1>; > }; > > + aoss_qmp: power-controller@c300000 { > + compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; > + reg = <0 0x0c300000 0 0x1000>; The QMP should only need 0x400 size [1]. Can you please change it so that when [1] goes in (and later when sleep stats enabled for sm6350 don't need to change size). [1] https://patchwork.kernel.org/project/linux-arm-msm/patch/1621596371-26482-4-git-send-email-mkshah@codeaurora.org/ Thanks, Maulik > + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + #clock-cells = <0>; > + #power-domain-cells = <1>; > + }; > + > tlmm: pinctrl@f100000 { > compatible = "qcom,sm6350-tlmm"; > reg = <0 0x0f100000 0 0x300000>;
Hi, On 8/28/2021 9:52 PM, Konrad Dybcio wrote: >>> + >>> + tcsr_mutex: hwlock@1f40000 { >>> + compatible = "qcom,tcsr-mutex"; >>> + reg = <0x0 0x01f40000 0x0 0x40000>; >>> + #hwlock-cells = <1>; >>> + }; >>> + >>> + pdc: interrupt-controller@b220000 { >>> + compatible = "qcom,sm6350-pdc", "qcom,pdc"; >>> + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; >> The second reg 0x17c000f0 is neither documented nor used in PDC irq chip driver. can you please remove it? >> >> Thanks, >> Maulik >> > Wouldn't it make more sense to keep it (like in other PDC-enabled SoCs' device trees) so that there's no > > need to add it back when the driver gains support for spi_configure_type (I believe that's what it's used for)? The second reg in some of the PDC enabled SoCs' went in since it may have slipped throgh code reviews when using downstream patch as is on upstream. Also the bindings document for PDC is still in txt, so yaml check could not catch the extra register which is not documented. An attempt to add support for spi_configure_type [1] & [2] had suggestion either to access second reg via mailbox or add another level of irqchip hierarchy between PDC to GIC to configure SPI type. Unless both [1] and [2] patch can go in as PDC irqchip driver won't gain support to use it. (using mailbox approch will have mailbox driver to access this register and PDC node may mention which mailbox to use). [1] https://patchwork.kernel.org/project/linux-arm-msm/patch/1568411962-1022-7-git-send-email-ilina@codeaurora.org/ [2] https://patchwork.kernel.org/project/linux-arm-msm/patch/1568411962-1022-8-git-send-email-ilina@codeaurora.org/ Thanks, Maulik > > > Konrad >
On Sat 28 Aug 08:18 CDT 2021, Konrad Dybcio wrote: > This is required for us to be able to access the associated registers, which > are (on at least some devices) gated by default. > Please either merge this with the patch that introduces the SMMU (which I presume causes this "issue") or introduce the SMMU earlier in the series. Regards, Bjorn > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index a3a1f0e63ace..95e69d9f8657 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -584,6 +584,7 @@ usb_1_dwc3: dwc3@a600000 { > compatible = "snps,dwc3"; > reg = <0 0x0a600000 0 0xcd00>; > interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0x540 0x0>; > snps,dis_u2_susphy_quirk; > snps,dis_enblslpm_quirk; > snps,has-lpm-erratum; > -- > 2.33.0 >
On Sat 28 Aug 08:18 CDT 2021, Konrad Dybcio wrote: > Add initial SM6350 SoC and Sony Xperia 10 III (PDX213, Lena platform) device > trees. There is no sign of another Lena devices on the horizon, so a common > DTSI is not created for now. 10 III features a Full HD OLED display and 5G > support, among other nice things like USB3. > Thanks for the series, looks quite nice, so please respin with the few small modifications noted in the reviews. > The bootloader is VERY unpleasant, to get a bootable setup you have to run: > > mkbootimg --kernel arch/arm64/boot/Image.gz --ramdisk [some initrd] \ > --dtb arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dtb \ > --cmdline "[some cmdline]" --base 0 --kernel_offset 0x8000 \ > --ramdisk_offset 0x1000000 --dtb_offset 0x1f00000 --os_version 11 \ > --os_patch_level "2021-08" --tags_offset 0x100 --pagesize 4096 \ > --header_version 2 -o mainline.img > > adb reboot bootloader > > // You have to either pull vbmeta{"","_system"} from > // /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process > fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img > fastboot --disable-verity --disable-verification flash vbmeta_system \ > vbmeta_system.img > > fastboot flash boot mainline.img > fastboot erase dtbo // This will take approx 70s... I always assumed that erase was broken when it took more than 5 seconds to clear the dtbo partition(s). So I always just flash a few kB of /dev/zero. Regards, Bjorn > fastboot reboot > > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > .../qcom/sm6350-sony-xperia-lena-pdx213.dts | 57 +++++++++++++++++++ > 2 files changed, 58 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 5bbeb058e1f2..d1ace2541ce1 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb > +dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb > diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts > new file mode 100644 > index 000000000000..a26c23754f5d > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts > @@ -0,0 +1,57 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> > + */ > +/dts-v1/; > + > +#include "sm6350.dtsi" > + > +/ { > + model = "Sony Xperia 10 III"; > + compatible = "sony,pdx213", "qcom,sm6350"; > + qcom,msm-id = <434 0x10000>, <459 0x10000>; > + qcom,board-id = <0x1000B 0>; > + > + chosen { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + framebuffer: framebuffer@a0000000 { > + compatible = "simple-framebuffer"; > + reg = <0 0xa0000000 0 0x2300000>; > + width = <1080>; > + height = <2520>; > + stride = <(1080 * 4)>; > + format = "a8r8g8b8"; > + clocks = <&gcc GCC_DISP_AXI_CLK>; > + }; > + }; > +}; > + > +&sdhc_2 { > + status = "okay"; > + > + cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; > +}; > + > +&tlmm { > + gpio-reserved-ranges = <13 4>, <45 2>, <56 2>; > +}; > + > +&usb_1 { > + status = "okay"; > +}; > + > +&usb_1_dwc3 { > + maximum-speed = "super-speed"; > + dr_mode = "peripheral"; > +}; > + > +&usb_1_hsphy { > + status = "okay"; > +}; > + > +&usb_1_qmpphy { > + status = "okay"; > +}; > -- > 2.33.0 >
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 9a2432a88074..897eec887e5a 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -171,6 +171,7 @@ properties: - qcom,kryo385 - qcom,kryo468 - qcom,kryo485 + - qcom,kryo560 - qcom,kryo685 - qcom,scorpion