| Message ID | 20210729053937.20281-2-shruthi.sanil@intel.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add the driver for Intel Keem Bay SoC timer block | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | success | |
| robh/dtbs-check | success |
On Thu, Jul 29, 2021 at 11:09:36AM +0530, shruthi.sanil@intel.com wrote: > From: Shruthi Sanil <shruthi.sanil@intel.com> > > Add Device Tree bindings for the Timer IP, which can be used as > clocksource and clockevent device in the Intel Keem Bay SoC. > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> > --- > .../bindings/timer/intel,keembay-timer.yaml | 166 ++++++++++++++++++ > 1 file changed, 166 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > new file mode 100644 > index 000000000000..b2eb2459d09b > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > @@ -0,0 +1,166 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel Keem Bay SoC Timers > + > +maintainers: > + - Shruthi Sanil <shruthi.sanil@intel.com> > + > +description: | > + The Intel Keem Bay timer driver supports 1 free running counter and 8 timers. > + Each timer is capable of generating inividual interrupt. > + Both the features are enabled through the timer general config register. > + > + The parent node represents the common general configuration details and > + the child nodes represents the counter and timers. > + > +properties: You need a 'compatible' here. Otherwise, how does one know what 'reg' contains. Also, without it, this schema will never be applied. > + reg: > + description: General configuration register address and length. > + maxItems: 1 > + > + ranges: true > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > +required: > + - reg > + - ranges > + - "#address-cells" > + - "#size-cells" > + > +patternProperties: > + "^counter@[0-9a-f]+$": > + type: object > + description: Properties for Intel Keem Bay counter > + > + properties: > + compatible: > + enum: > + - intel,keembay-counter > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - clocks > + > + "^timer@[0-9a-f]+$": > + type: object > + description: Properties for Intel Keem Bay timer > + > + properties: > + compatible: > + enum: > + - intel,keembay-timer > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #define KEEM_BAY_A53_TIM > + > + soc { > + #address-cells = <0x2>; > + #size-cells = <0x2>; > + > + gpt@20331000 { > + reg = <0x0 0x20331000 0x0 0xc>; > + ranges = <0x0 0x0 0x20330000 0xF0>; > + #address-cells = <0x1>; > + #size-cells = <0x1>; > + > + counter@e8 { > + compatible = "intel,keembay-counter"; > + reg = <0xe8 0x8>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + > + timer@10 { > + compatible = "intel,keembay-timer"; > + reg = <0x10 0xc>; > + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + > + timer@20 { > + compatible = "intel,keembay-timer"; > + reg = <0x20 0xc>; > + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + > + timer@30 { > + compatible = "intel,keembay-timer"; > + reg = <0x30 0xc>; > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + > + timer@40 { > + compatible = "intel,keembay-timer"; > + reg = <0x40 0xc>; > + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + > + timer@50 { > + compatible = "intel,keembay-timer"; > + reg = <0x50 0xc>; > + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + > + timer@60 { > + compatible = "intel,keembay-timer"; > + reg = <0x60 0xc>; > + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + > + timer@70 { > + compatible = "intel,keembay-timer"; > + reg = <0x70 0xc>; > + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + > + timer@80 { > + compatible = "intel,keembay-timer"; > + reg = <0x80 0xc>; > + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + }; > + }; > + > +... > -- > 2.17.1 > >
> -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Tuesday, August 3, 2021 4:14 AM > To: Sanil, Shruthi <shruthi.sanil@intel.com> > Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux- > kernel@vger.kernel.org; devicetree@vger.kernel.org; > andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com; > mgross@linux.intel.com; Thokala, Srikanth <srikanth.thokala@intel.com>; > Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>; > Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com> > Subject: Re: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel Keem > Bay SoC Timer > > On Thu, Jul 29, 2021 at 11:09:36AM +0530, shruthi.sanil@intel.com wrote: > > From: Shruthi Sanil <shruthi.sanil@intel.com> > > > > Add Device Tree bindings for the Timer IP, which can be used as > > clocksource and clockevent device in the Intel Keem Bay SoC. > > > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> > > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> > > --- > > .../bindings/timer/intel,keembay-timer.yaml | 166 ++++++++++++++++++ > > 1 file changed, 166 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > new file mode 100644 > > index 000000000000..b2eb2459d09b > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/timer/intel,keembay- > timer.yaml > > @@ -0,0 +1,166 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Intel Keem Bay SoC Timers > > + > > +maintainers: > > + - Shruthi Sanil <shruthi.sanil@intel.com> > > + > > +description: | > > + The Intel Keem Bay timer driver supports 1 free running counter and 8 > timers. > > + Each timer is capable of generating inividual interrupt. > > + Both the features are enabled through the timer general config register. > > + > > + The parent node represents the common general configuration details > > + and the child nodes represents the counter and timers. > > + > > +properties: > > You need a 'compatible' here. Otherwise, how does one know what 'reg' > contains. Also, without it, this schema will never be applied. > This is a parent block that has the common configuration register address defined which we would need during the initialization of the child nodes. This block in itself is not doing anything. We have this because, we have a common register that is required to be accessed during all the timers and counter initialization. The child nodes have the compatible string, which is used in the driver. I have validated this on the Keem Bay HW and see that the timer probes are being called and the timers are functional as expected. > > + reg: > > + description: General configuration register address and length. > > + maxItems: 1 > > + > > + ranges: true > > + > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > + > > +required: > > + - reg > > + - ranges > > + - "#address-cells" > > + - "#size-cells" > > + > > +patternProperties: > > + "^counter@[0-9a-f]+$": > > + type: object > > + description: Properties for Intel Keem Bay counter > > + > > + properties: > > + compatible: > > + enum: > > + - intel,keembay-counter > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + required: > > + - compatible > > + - reg > > + - clocks > > + > > + "^timer@[0-9a-f]+$": > > + type: object > > + description: Properties for Intel Keem Bay timer > > + > > + properties: > > + compatible: > > + enum: > > + - intel,keembay-timer > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #define KEEM_BAY_A53_TIM > > + > > + soc { > > + #address-cells = <0x2>; > > + #size-cells = <0x2>; > > + > > + gpt@20331000 { > > + reg = <0x0 0x20331000 0x0 0xc>; > > + ranges = <0x0 0x0 0x20330000 0xF0>; > > + #address-cells = <0x1>; > > + #size-cells = <0x1>; > > + > > + counter@e8 { > > + compatible = "intel,keembay-counter"; > > + reg = <0xe8 0x8>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@10 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x10 0xc>; > > + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@20 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x20 0xc>; > > + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@30 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x30 0xc>; > > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@40 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x40 0xc>; > > + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@50 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x50 0xc>; > > + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@60 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x60 0xc>; > > + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@70 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x70 0xc>; > > + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@80 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x80 0xc>; > > + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + }; > > + }; > > + > > +... > > -- > > 2.17.1 > > > >
On Wed, Aug 4, 2021 at 8:35 AM Sanil, Shruthi <shruthi.sanil@intel.com> wrote: > > From: Rob Herring <robh@kernel.org> > > Sent: Tuesday, August 3, 2021 4:14 AM ... > > > +properties: > > > > You need a 'compatible' here. Otherwise, how does one know what 'reg' > > contains. Also, without it, this schema will never be applied. > > > > This is a parent block that has the common configuration register address defined which we would need during the initialization of the child nodes. This block in itself is not doing anything. We have this because, we have a common register that is required to be accessed during all the timers and counter initialization. > The child nodes have the compatible string, which is used in the driver. I have validated this on the Keem Bay HW and see that the timer probes are being called and the timers are functional as expected. I think I understand now. The problem is that the current state of affairs with this block is incorrect software representation. What you need is to create an MFD device driver (for which the compatible will exactly the one Rob is telling about) and from it you register the rest of your drivers. The existing drivers for this block should be converted to MFD schema.
> -----Original Message----- > From: Andy Shevchenko <andy.shevchenko@gmail.com> > Sent: Wednesday, August 4, 2021 1:08 PM > To: Sanil, Shruthi <shruthi.sanil@intel.com> > Cc: Rob Herring <robh@kernel.org>; daniel.lezcano@linaro.org; > tglx@linutronix.de; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; andriy.shevchenko@linux.intel.com; > kris.pan@linux.intel.com; mgross@linux.intel.com; Thokala, Srikanth > <srikanth.thokala@intel.com>; Raja Subramanian, Lakshmi Bai > <lakshmi.bai.raja.subramanian@intel.com>; Sangannavar, Mallikarjunappa > <mallikarjunappa.sangannavar@intel.com> > Subject: Re: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel Keem > Bay SoC Timer > > On Wed, Aug 4, 2021 at 8:35 AM Sanil, Shruthi <shruthi.sanil@intel.com> > wrote: > > > From: Rob Herring <robh@kernel.org> > > > Sent: Tuesday, August 3, 2021 4:14 AM > > ... > > > > > +properties: > > > > > > You need a 'compatible' here. Otherwise, how does one know what 'reg' > > > contains. Also, without it, this schema will never be applied. > > > > > > > This is a parent block that has the common configuration register address > defined which we would need during the initialization of the child nodes. This > block in itself is not doing anything. We have this because, we have a > common register that is required to be accessed during all the timers and > counter initialization. > > The child nodes have the compatible string, which is used in the driver. I > have validated this on the Keem Bay HW and see that the timer probes are > being called and the timers are functional as expected. > > I think I understand now. The problem is that the current state of affairs with > this block is incorrect software representation. What you need is to create an > MFD device driver (for which the compatible will exactly the one Rob is telling > about) and from it you register the rest of your drivers. The existing drivers > for this block should be converted to MFD schema. Sure Andy, I shall check on this and get back. Thank You! > > -- > With Best Regards, > Andy Shevchenko
> -----Original Message----- > From: Sanil, Shruthi > Sent: Thursday, August 12, 2021 10:19 PM > To: Andy Shevchenko <andy.shevchenko@gmail.com> > Cc: Rob Herring <robh@kernel.org>; daniel.lezcano@linaro.org; > tglx@linutronix.de; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; andriy.shevchenko@linux.intel.com; > kris.pan@linux.intel.com; mgross@linux.intel.com; Thokala, Srikanth > <Srikanth.Thokala@intel.com>; Raja Subramanian, Lakshmi Bai > <lakshmi.bai.raja.subramanian@intel.com>; Sangannavar, Mallikarjunappa > <mallikarjunappa.sangannavar@intel.com> > Subject: RE: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel Keem > Bay SoC Timer > > > -----Original Message----- > > From: Andy Shevchenko <andy.shevchenko@gmail.com> > > Sent: Wednesday, August 4, 2021 1:08 PM > > To: Sanil, Shruthi <shruthi.sanil@intel.com> > > Cc: Rob Herring <robh@kernel.org>; daniel.lezcano@linaro.org; > > tglx@linutronix.de; linux-kernel@vger.kernel.org; > > devicetree@vger.kernel.org; andriy.shevchenko@linux.intel.com; > > kris.pan@linux.intel.com; mgross@linux.intel.com; Thokala, Srikanth > > <srikanth.thokala@intel.com>; Raja Subramanian, Lakshmi Bai > > <lakshmi.bai.raja.subramanian@intel.com>; Sangannavar, Mallikarjunappa > > <mallikarjunappa.sangannavar@intel.com> > > Subject: Re: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel > > Keem Bay SoC Timer > > > > On Wed, Aug 4, 2021 at 8:35 AM Sanil, Shruthi > > <shruthi.sanil@intel.com> > > wrote: > > > > From: Rob Herring <robh@kernel.org> > > > > Sent: Tuesday, August 3, 2021 4:14 AM > > > > ... > > > > > > > +properties: > > > > > > > > You need a 'compatible' here. Otherwise, how does one know what > 'reg' > > > > contains. Also, without it, this schema will never be applied. > > > > > > > > > > This is a parent block that has the common configuration register > > > address > > defined which we would need during the initialization of the child > > nodes. This block in itself is not doing anything. We have this > > because, we have a common register that is required to be accessed > > during all the timers and counter initialization. > > > The child nodes have the compatible string, which is used in the > > > driver. I > > have validated this on the Keem Bay HW and see that the timer probes > > are being called and the timers are functional as expected. > > > > I think I understand now. The problem is that the current state of > > affairs with this block is incorrect software representation. What you > > need is to create an MFD device driver (for which the compatible will > > exactly the one Rob is telling > > about) and from it you register the rest of your drivers. The existing > > drivers for this block should be converted to MFD schema. > > Sure Andy, I shall check on this and get back. > Thank You! > Hi Rob, Do you agree with the above proposal of creating a MFD device with compatible string "simple-mfd"? > > > > -- > > With Best Regards, > > Andy Shevchenko
diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml new file mode 100644 index 000000000000..b2eb2459d09b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay SoC Timers + +maintainers: + - Shruthi Sanil <shruthi.sanil@intel.com> + +description: | + The Intel Keem Bay timer driver supports 1 free running counter and 8 timers. + Each timer is capable of generating inividual interrupt. + Both the features are enabled through the timer general config register. + + The parent node represents the common general configuration details and + the child nodes represents the counter and timers. + +properties: + reg: + description: General configuration register address and length. + maxItems: 1 + + ranges: true + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + +required: + - reg + - ranges + - "#address-cells" + - "#size-cells" + +patternProperties: + "^counter@[0-9a-f]+$": + type: object + description: Properties for Intel Keem Bay counter + + properties: + compatible: + enum: + - intel,keembay-counter + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + required: + - compatible + - reg + - clocks + + "^timer@[0-9a-f]+$": + type: object + description: Properties for Intel Keem Bay timer + + properties: + compatible: + enum: + - intel,keembay-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #define KEEM_BAY_A53_TIM + + soc { + #address-cells = <0x2>; + #size-cells = <0x2>; + + gpt@20331000 { + reg = <0x0 0x20331000 0x0 0xc>; + ranges = <0x0 0x0 0x20330000 0xF0>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + counter@e8 { + compatible = "intel,keembay-counter"; + reg = <0xe8 0x8>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@10 { + compatible = "intel,keembay-timer"; + reg = <0x10 0xc>; + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@20 { + compatible = "intel,keembay-timer"; + reg = <0x20 0xc>; + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@30 { + compatible = "intel,keembay-timer"; + reg = <0x30 0xc>; + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@40 { + compatible = "intel,keembay-timer"; + reg = <0x40 0xc>; + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@50 { + compatible = "intel,keembay-timer"; + reg = <0x50 0xc>; + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@60 { + compatible = "intel,keembay-timer"; + reg = <0x60 0xc>; + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@70 { + compatible = "intel,keembay-timer"; + reg = <0x70 0xc>; + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@80 { + compatible = "intel,keembay-timer"; + reg = <0x80 0xc>; + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + }; + }; + +...