diff mbox series

dt-bindings: serial: convert Cadence UART bindings to YAML

Message ID 20210613213359.296400-1-iwamatsu@nigauri.org
State Changes Requested, archived
Headers show
Series dt-bindings: serial: convert Cadence UART bindings to YAML | expand

Checks

Context Check Description
robh/checkpatch warning total: 0 errors, 2 warnings, 68 lines checked
robh/dt-meta-schema fail build log

Commit Message

Nobuhiro Iwamatsu June 13, 2021, 9:33 p.m. UTC
Convert serial for Cadence UART bindings documentation to YAML.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 .../devicetree/bindings/serial/cdns,uart.txt  | 27 --------
 .../devicetree/bindings/serial/cdns,uart.yaml | 68 +++++++++++++++++++
 2 files changed, 68 insertions(+), 27 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/serial/cdns,uart.txt
 create mode 100644 Documentation/devicetree/bindings/serial/cdns,uart.yaml

Comments

Rob Herring (Arm) June 14, 2021, 1:39 p.m. UTC | #1
On Mon, 14 Jun 2021 06:33:59 +0900, Nobuhiro Iwamatsu wrote:
> Convert serial for Cadence UART bindings documentation to YAML.
> 
> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> ---
>  .../devicetree/bindings/serial/cdns,uart.txt  | 27 --------
>  .../devicetree/bindings/serial/cdns,uart.yaml | 68 +++++++++++++++++++
>  2 files changed, 68 insertions(+), 27 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/serial/cdns,uart.txt
>  create mode 100644 Documentation/devicetree/bindings/serial/cdns,uart.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/serial/cdns,uart.yaml:21:13: [warning] wrong indentation: expected 14 but found 12 (indentation)
./Documentation/devicetree/bindings/serial/cdns,uart.yaml:26:13: [warning] wrong indentation: expected 14 but found 12 (indentation)

dtschema/dtc warnings/errors:
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1491509

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
Rob Herring (Arm) June 14, 2021, 3:03 p.m. UTC | #2
On Mon, Jun 14, 2021 at 06:33:59AM +0900, Nobuhiro Iwamatsu wrote:
> Convert serial for Cadence UART bindings documentation to YAML.
> 
> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> ---
>  .../devicetree/bindings/serial/cdns,uart.txt  | 27 --------
>  .../devicetree/bindings/serial/cdns,uart.yaml | 68 +++++++++++++++++++
>  2 files changed, 68 insertions(+), 27 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/serial/cdns,uart.txt
>  create mode 100644 Documentation/devicetree/bindings/serial/cdns,uart.yaml
> 
> diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.txt b/Documentation/devicetree/bindings/serial/cdns,uart.txt
> deleted file mode 100644
> index 4efc560f90abbd..00000000000000
> --- a/Documentation/devicetree/bindings/serial/cdns,uart.txt
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -Binding for Cadence UART Controller
> -
> -Required properties:
> -- compatible :
> -  Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
> -  Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
> -- reg: Should contain UART controller registers location and length.
> -- interrupts: Should contain UART controller interrupts.
> -- clocks: Must contain phandles to the UART clocks
> -  See ../clocks/clock-bindings.txt for details.
> -- clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
> -  See ../clocks/clock-bindings.txt for details.
> -
> -
> -Optional properties:
> -- cts-override : Override the CTS modem status signal. This signal will
> -  always be reported as active instead of being obtained from the modem status
> -  register. Define this if your serial port does not use this pin
> -
> -Example:
> -	uart@e0000000 {
> -		compatible = "cdns,uart-r1p8";
> -		clocks = <&clkc 23>, <&clkc 40>;
> -		clock-names = "uart_clk", "pclk";
> -		reg = <0xE0000000 0x1000>;
> -		interrupts = <0 27 4>;
> -	};
> diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
> new file mode 100644
> index 00000000000000..ce467fa464bfd0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence UART Controller Device Tree Bindings
> +
> +maintainers:
> +  - Michal Simek <michal.simek@xilinx.com>
> +
> +allOf:
> +  - $ref: /schemas/serial.yaml#
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - description: UART controller for Zynq-7xxx SoC
> +        items:
> +          - enum:
> +            - xlnx,xuartps
> +            - cdns,uart-r1p8

What you want is:

items:
  - const: xlnx,xuartps
  - const: cdns,uart-r1p8

> +      - description: UART controller for Zynq Ultrascale+ MPSoC
> +        items:
> +          - enum:
> +            - xlnx,zynqmp-uart
> +            - cdns,uart-r1p12
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 2
> +
> +  clock-names:
> +    items:
> +      - const: uart_clk
> +      - const: pclk
> +
> +  cts-override:
> +    description: |
> +      Override the CTS modem status signal. This signal will
> +      always be reported as active instead of being obtained
> +      from the modem status register. Define this if your serial
> +      port does not use this pin.
> +    type: boolean
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false

unevaluatedProperties: false

because you could have child nodes with attached devices.

> +
> +examples:
> +  - |
> +    serial@e0000000 {
> +      compatible = "cdns,uart-r1p8";

This is wrong based on what the binding said.

> +      clocks = <&clkc 23>, <&clkc 40>;
> +      clock-names = "uart_clk", "pclk";
> +      reg = <0xE0000000 0x1000>;
> +      interrupts = <0 27 4>;
> +    };
> -- 
> 2.32.0
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.txt b/Documentation/devicetree/bindings/serial/cdns,uart.txt
deleted file mode 100644
index 4efc560f90abbd..00000000000000
--- a/Documentation/devicetree/bindings/serial/cdns,uart.txt
+++ /dev/null
@@ -1,27 +0,0 @@ 
-Binding for Cadence UART Controller
-
-Required properties:
-- compatible :
-  Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
-  Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
-- reg: Should contain UART controller registers location and length.
-- interrupts: Should contain UART controller interrupts.
-- clocks: Must contain phandles to the UART clocks
-  See ../clocks/clock-bindings.txt for details.
-- clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
-  See ../clocks/clock-bindings.txt for details.
-
-
-Optional properties:
-- cts-override : Override the CTS modem status signal. This signal will
-  always be reported as active instead of being obtained from the modem status
-  register. Define this if your serial port does not use this pin
-
-Example:
-	uart@e0000000 {
-		compatible = "cdns,uart-r1p8";
-		clocks = <&clkc 23>, <&clkc 40>;
-		clock-names = "uart_clk", "pclk";
-		reg = <0xE0000000 0x1000>;
-		interrupts = <0 27 4>;
-	};
diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
new file mode 100644
index 00000000000000..ce467fa464bfd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
@@ -0,0 +1,68 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence UART Controller Device Tree Bindings
+
+maintainers:
+  - Michal Simek <michal.simek@xilinx.com>
+
+allOf:
+  - $ref: /schemas/serial.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - description: UART controller for Zynq-7xxx SoC
+        items:
+          - enum:
+            - xlnx,xuartps
+            - cdns,uart-r1p8
+      - description: UART controller for Zynq Ultrascale+ MPSoC
+        items:
+          - enum:
+            - xlnx,zynqmp-uart
+            - cdns,uart-r1p12
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: uart_clk
+      - const: pclk
+
+  cts-override:
+    description: |
+      Override the CTS modem status signal. This signal will
+      always be reported as active instead of being obtained
+      from the modem status register. Define this if your serial
+      port does not use this pin.
+    type: boolean
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    serial@e0000000 {
+      compatible = "cdns,uart-r1p8";
+      clocks = <&clkc 23>, <&clkc 40>;
+      clock-names = "uart_clk", "pclk";
+      reg = <0xE0000000 0x1000>;
+      interrupts = <0 27 4>;
+    };