From patchwork Wed Jun 9 14:55:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 1489934 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4G0VXs04z5z9sVt for ; Thu, 10 Jun 2021 00:55:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238571AbhFIO5t (ORCPT ); Wed, 9 Jun 2021 10:57:49 -0400 Received: from relay08.th.seeweb.it ([5.144.164.169]:51631 "EHLO relay08.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238492AbhFIO5r (ORCPT ); Wed, 9 Jun 2021 10:57:47 -0400 Received: from localhost.localdomain (83.6.168.161.neoplus.adsl.tpnet.pl [83.6.168.161]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 191803F629; Wed, 9 Jun 2021 16:55:49 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 9/9] clk: qcom: gcc-msm8994: Add a quirk for a different SDCC configuration Date: Wed, 9 Jun 2021 16:55:21 +0200 Message-Id: <20210609145523.467090-9-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210609145523.467090-1-konrad.dybcio@somainline.org> References: <20210609145523.467090-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some devices come with a different SDCC clock configuration, account for that. Signed-off-by: Konrad Dybcio Acked-by: Rob Herring --- .../bindings/clock/qcom,gcc-msm8994.yaml | 4 ++++ drivers/clk/qcom/gcc-msm8994.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml index b44a844d894c..4ba2f72d3cad 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml @@ -49,6 +49,10 @@ properties: description: Protected clock specifier list as per common clock binding. + qcom,sdcc2-clk-src-40mhz: + description: SDCC2_APPS clock source runs at 40MHz. + type: boolean + required: - compatible - reg diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index bc8ad4973dd9..4903b07964dc 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -1012,6 +1012,19 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { }, }; +static struct freq_tbl ftbl_sdcc2_40mhz_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 15, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(40000000, P_GPLL0, 15, 0, 0), + F(50000000, P_GPLL0, 12, 0, 0), + F(80000000, P_GPLL0, 7.5, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(200000000, P_GPLL0, 3, 0, 0), + { } +}; + static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { F(144000, P_XO, 16, 3, 25), F(400000, P_XO, 12, 1, 4), @@ -2788,6 +2801,9 @@ static int gcc_msm8994_probe(struct platform_device *pdev) gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL; } + if (of_find_property(dev->of_node, "qcom,sdcc2-clk-src-40mhz", NULL)) + sdcc2_apps_clk_src.freq_tbl = ftbl_sdcc2_40mhz_apps_clk_src; + return qcom_cc_probe(pdev, &gcc_msm8994_desc); }