diff mbox series

dt-bindings: display: bridge: lvds-codec: Fix spacing

Message ID 20210515203932.366799-1-marex@denx.de
State Changes Requested
Headers show
Series dt-bindings: display: bridge: lvds-codec: Fix spacing | expand

Checks

Context Check Description
robh/checkpatch success
robh/dt-meta-schema success
robh/dtbs-check fail build log

Commit Message

Marek Vasut May 15, 2021, 8:39 p.m. UTC
Add missing spaces to make the diagrams readable, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: devicetree@vger.kernel.org
To: dri-devel@lists.freedesktop.org
---
 .../devicetree/bindings/display/panel/lvds.yaml      | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Laurent Pinchart May 15, 2021, 9:48 p.m. UTC | #1
Hi Marek,

Thank you for the patch.

On Sat, May 15, 2021 at 10:39:32PM +0200, Marek Vasut wrote:
> Add missing spaces to make the diagrams readable, no functional change.

Looks better indeed. The patch view looks bad though, because of the
tabs. Maybe you could replace them with spaces, while at it ?

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sam Ravnborg <sam@ravnborg.org>
> Cc: devicetree@vger.kernel.org
> To: dri-devel@lists.freedesktop.org
> ---
>  .../devicetree/bindings/display/panel/lvds.yaml      | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/panel/lvds.yaml b/Documentation/devicetree/bindings/display/panel/lvds.yaml
> index 31164608ba1d..06d7ca692d0d 100644
> --- a/Documentation/devicetree/bindings/display/panel/lvds.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/lvds.yaml
> @@ -52,9 +52,9 @@ properties:
>          [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
>  
>        Slot	    0       1       2       3       4       5       6
> -            ________________                         _________________
> +                ________________                         _________________
>        Clock	                \_______________________/
> -              ______  ______  ______  ______  ______  ______  ______
> +                  ______  ______  ______  ______  ______  ______  ______
>        DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
>        DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
>        DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
> @@ -63,9 +63,9 @@ properties:
>          specifications. Data are transferred as follows on 4 LVDS lanes.
>  
>        Slot	    0       1       2       3       4       5       6
> -            ________________                         _________________
> +                ________________                         _________________
>        Clock	                \_______________________/
> -              ______  ______  ______  ______  ______  ______  ______
> +                  ______  ______  ______  ______  ______  ______  ______
>        DATA0	><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
>        DATA1	><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
>        DATA2	><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
> @@ -75,9 +75,9 @@ properties:
>          Data are transferred as follows on 4 LVDS lanes.
>  
>        Slot	    0       1       2       3       4       5       6
> -            ________________                         _________________
> +                ________________                         _________________
>        Clock	                \_______________________/
> -              ______  ______  ______  ______  ______  ______  ______
> +                  ______  ______  ______  ______  ______  ______  ______
>        DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
>        DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
>        DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
Marek Vasut May 15, 2021, 11:49 p.m. UTC | #2
On 5/15/21 11:48 PM, Laurent Pinchart wrote:
> Hi Marek,

Hi,

> Thank you for the patch.
> 
> On Sat, May 15, 2021 at 10:39:32PM +0200, Marek Vasut wrote:
>> Add missing spaces to make the diagrams readable, no functional change.
> 
> Looks better indeed. The patch view looks bad though, because of the
> tabs. Maybe you could replace them with spaces, while at it ?

It is all spaces, where do you see tabs ?

[...]
Laurent Pinchart May 16, 2021, 12:46 a.m. UTC | #3
Hi Marek,

On Sun, May 16, 2021 at 01:49:11AM +0200, Marek Vasut wrote:
> On 5/15/21 11:48 PM, Laurent Pinchart wrote:
> > Hi Marek,
> 
> Hi,
> 
> > Thank you for the patch.
> > 
> > On Sat, May 15, 2021 at 10:39:32PM +0200, Marek Vasut wrote:
> >> Add missing spaces to make the diagrams readable, no functional change.
> > 
> > Looks better indeed. The patch view looks bad though, because of the
> > tabs. Maybe you could replace them with spaces, while at it ?
> 
> It is all spaces, where do you see tabs ?

Right after "Slot", "Clock" and "DATA[0123]". You're not touching those
lines, but having tabs there messes up the formatting of the patch
itself (the resulting bindings file looks good).

By the way, the subject line doesn't match the patch, you're modifying
panel/lvds.yaml, not bridge/lvds-codec.yaml.
Rob Herring May 18, 2021, 12:59 p.m. UTC | #4
On Sun, May 16, 2021 at 12:48:05AM +0300, Laurent Pinchart wrote:
> Hi Marek,
> 
> Thank you for the patch.
> 
> On Sat, May 15, 2021 at 10:39:32PM +0200, Marek Vasut wrote:
> > Add missing spaces to make the diagrams readable, no functional change.
> 
> Looks better indeed. The patch view looks bad though, because of the
> tabs. Maybe you could replace them with spaces, while at it ?

It's best to not have tabs in yaml. And if we ever generate any 
documentation out of the schema, the tabs would probably cause issues.

Rob
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/display/panel/lvds.yaml b/Documentation/devicetree/bindings/display/panel/lvds.yaml
index 31164608ba1d..06d7ca692d0d 100644
--- a/Documentation/devicetree/bindings/display/panel/lvds.yaml
+++ b/Documentation/devicetree/bindings/display/panel/lvds.yaml
@@ -52,9 +52,9 @@  properties:
         [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
 
       Slot	    0       1       2       3       4       5       6
-            ________________                         _________________
+                ________________                         _________________
       Clock	                \_______________________/
-              ______  ______  ______  ______  ______  ______  ______
+                  ______  ______  ______  ______  ______  ______  ______
       DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
       DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
       DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
@@ -63,9 +63,9 @@  properties:
         specifications. Data are transferred as follows on 4 LVDS lanes.
 
       Slot	    0       1       2       3       4       5       6
-            ________________                         _________________
+                ________________                         _________________
       Clock	                \_______________________/
-              ______  ______  ______  ______  ______  ______  ______
+                  ______  ______  ______  ______  ______  ______  ______
       DATA0	><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
       DATA1	><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
       DATA2	><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
@@ -75,9 +75,9 @@  properties:
         Data are transferred as follows on 4 LVDS lanes.
 
       Slot	    0       1       2       3       4       5       6
-            ________________                         _________________
+                ________________                         _________________
       Clock	                \_______________________/
-              ______  ______  ______  ______  ______  ______  ______
+                  ______  ______  ______  ______  ______  ______  ______
       DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
       DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
       DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><