diff mbox series

[2/2] dt-bindings: gpio: stp: add gphy3 and gphy4 properties

Message ID 20210513210340.10466-2-olek2@wp.pl
State Changes Requested
Headers show
Series [1/2] dt-bindings: gpio: stp: convert to json-schema | expand

Checks

Context Check Description
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robh/dt-meta-schema success
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Commit Message

Aleksander Jan Bajkowski May 13, 2021, 9:03 p.m. UTC
The xRX300 family has 3 and the xRX330 has 4 gphs. They can also control
some pins of the gpio cascade. This patch documents the missing properties.

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
 .../devicetree/bindings/gpio/gpio-stp-xway.yaml  | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Rob Herring May 18, 2021, 1:19 a.m. UTC | #1
On Thu, May 13, 2021 at 11:03:40PM +0200, Aleksander Jan Bajkowski wrote:
> The xRX300 family has 3 and the xRX330 has 4 gphs. They can also control
> some pins of the gpio cascade. This patch documents the missing properties.
> 
> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
> ---
>  .../devicetree/bindings/gpio/gpio-stp-xway.yaml  | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
> index a36acc98898c..beb755edf639 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
> +++ b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
> @@ -84,6 +84,22 @@ properties:
>      minimum: 0x0
>      maximum: 0x7
>  
> +  lantiq,phy3:
> +    description:
> +      The gphy3 core can control 3 bits of the gpio cascade. Available on
> +      the xRX300 and xRX330 family.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0x0
> +    maximum: 0x7
> +
> +  lantiq,phy4:

You could make these a pattern under patternProperties instead.

> +    description:
> +      The gphy4 core can control 3 bits of the gpio cascade. Available on
> +      the xRX330 family.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0x0
> +    maximum: 0x7
> +
>    lantiq,rising:
>      description:
>        Use rising instead of falling edge for the shift register.
> -- 
> 2.30.2
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
index a36acc98898c..beb755edf639 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
+++ b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
@@ -84,6 +84,22 @@  properties:
     minimum: 0x0
     maximum: 0x7
 
+  lantiq,phy3:
+    description:
+      The gphy3 core can control 3 bits of the gpio cascade. Available on
+      the xRX300 and xRX330 family.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0x0
+    maximum: 0x7
+
+  lantiq,phy4:
+    description:
+      The gphy4 core can control 3 bits of the gpio cascade. Available on
+      the xRX330 family.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0x0
+    maximum: 0x7
+
   lantiq,rising:
     description:
       Use rising instead of falling edge for the shift register.