| Message ID | 20200907031724.3512099-2-f.fainelli@gmail.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | bus: brcmstb_gisb: Add support for breakpoint interrupts | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt index 729def62f0c5..10f6d0a8159d 100644 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt @@ -10,7 +10,8 @@ Required properties: "brcm,bcm7038-gisb-arb" for 130nm chips - reg: specifies the base physical address and size of the registers - interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller + the parent interrupt controller. A third optional interrupt may be specified + for breakpoints. Optional properties:
The GISB arbiter can have a third and optional interrupt to handle GISB breakpoints. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)