From patchwork Wed Aug 19 03:42:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark-PK Tsai X-Patchwork-Id: 1347426 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=RfSu+rcZ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BWYWv3BGVz9sTW for ; Wed, 19 Aug 2020 13:42:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726783AbgHSDmu (ORCPT ); Tue, 18 Aug 2020 23:42:50 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:14811 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726318AbgHSDms (ORCPT ); Tue, 18 Aug 2020 23:42:48 -0400 X-UUID: 5160d2c900fd46c3838dbea551d4a832-20200819 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=kpBsxONTkkbc5bOYHR9hFMap17MiXFktP1dZs/pBlQA=; b=RfSu+rcZUd3Cub/Xyz1jxH+TTd6MqM4ZtiXa3/zxdvv76GbCWgR25ZQ35bQz/wG0L+4OInFwm6XTG7K1ADSxbeQYBv0hhl/4SsyVGEOuGarLMt9RlMQKbKO4hmOFIo0lRk//LBHrIkXyvEBCXtrg30LGtwwra3NtPjCdbSLVEC4=; X-UUID: 5160d2c900fd46c3838dbea551d4a832-20200819 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1897202186; Wed, 19 Aug 2020 11:42:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 19 Aug 2020 11:42:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 19 Aug 2020 11:42:40 +0800 From: Mark-PK Tsai To: CC: , , , , , , , , , , , Subject: [PATCH 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller Date: Wed, 19 Aug 2020 11:42:31 +0800 Message-ID: <20200819034231.20726-3-mark-pk.tsai@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200819034231.20726-1-mark-pk.tsai@mediatek.com> References: <20200819034231.20726-1-mark-pk.tsai@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for MStar interrupt controller. Signed-off-by: Mark-PK Tsai --- .../interrupt-controller/mstar,mst-intc.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml new file mode 100644 index 000000000000..6e383315e529 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar Interrupt Controller + +maintainers: + - Mark-PK Tsai + +description: |+ + MStar, SigmaStar and Mediatek DTV SoCs contain multiple legacy + interrupt controllers that routes interrupts to the GIC. + + The HW block exposes a number of interrupt controllers, each + can support up to 64 interrupts. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - const: mstar,mst-intc + - enum: + - mediatek,mt58xx-intc + + interrupt-controller: true + + "#address-cells": + enum: [ 0, 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + "#interrupt-cells": + const: 3 + description: | + Use the same format as specified by GIC in arm,gic.yaml. + + reg: + description: | + Physical base address of the mstar interrupt controller + registers and length of memory mapped region. + minItems: 1 + + mstar,irqs-map-range: + description: | + The range of parent interrupt controller's interrupt lines + that are hardwired to mstar interrupt controller. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + minItems: 2 + maxItems: 2 + + mstar,intc-no-eoi: + description: | + Mark this controller has no End Of Interrupt(EOI) implementation. + This is a empty, boolean property. + type: boolean + +required: + - compatible + - reg + - mstar,irqs-map-range + +additionalProperties: false + +examples: + - | + mst_intc0: interrupt-controller@1f2032d0 { + compatible = "mstar,mst-intc", "mediatek,mt58xx-intc"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + reg = <0x1f2032d0 0x30>; + mstar,irqs-map-range = <0 63>; + }; +...