| Message ID | 20200202211827.27682-12-f.fainelli@gmail.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | dt-bindings: arm: bcm: Convert boards to YAML | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | "total: 0 errors, 6 warnings, 22 lines checked" |
| robh/checkpatch | warning | "total: 0 errors, 6 warnings, 22 lines checked" |
| robh/dt-meta-schema | success |
On Sun, Feb 02, 2020 at 01:18:26PM -0800, Florian Fainelli wrote: > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml > index c23c24ff7575..6f56a623c1cd 100644 > --- a/Documentation/devicetree/bindings/arm/cpus.yaml > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml > @@ -272,6 +272,22 @@ properties: > While optional, it is the preferred way to get access to > the cpu-core power-domains. > > + secondary-boot-reg: > + $ref: '/schemas/types.yaml#/definitions/uint32' > + description: | > + Required for systems that have an "enable-method" property value of > + "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". > + > + This includes the following SoCs: | > + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 > + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 > + > + The secondary-boot-reg property is a u32 value that specifies the > + physical address of the register used to request the ROM holding pen > + code release a secondary CPU. The value written to the register is > + formed by encoding the target CPU id into the low bits of the > + physical start address it should jump to. > + You can make the requirement explicit (and enforced by the schemas) using: if: properties: enable-method: contains: enum: - brcm,bcm11351-cpu-method - brcm,bcm23550 - brcm,bcm-nsp-smp then: required: - secondary-boot-reg Maxime
On 2/3/2020 12:34 AM, Maxime Ripard wrote: > On Sun, Feb 02, 2020 at 01:18:26PM -0800, Florian Fainelli wrote: >> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml >> index c23c24ff7575..6f56a623c1cd 100644 >> --- a/Documentation/devicetree/bindings/arm/cpus.yaml >> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml >> @@ -272,6 +272,22 @@ properties: >> While optional, it is the preferred way to get access to >> the cpu-core power-domains. >> >> + secondary-boot-reg: >> + $ref: '/schemas/types.yaml#/definitions/uint32' >> + description: | >> + Required for systems that have an "enable-method" property value of >> + "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". >> + >> + This includes the following SoCs: | >> + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 >> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 >> + >> + The secondary-boot-reg property is a u32 value that specifies the >> + physical address of the register used to request the ROM holding pen >> + code release a secondary CPU. The value written to the register is >> + formed by encoding the target CPU id into the low bits of the >> + physical start address it should jump to. >> + > > You can make the requirement explicit (and enforced by the schemas) using: > > if: > properties: > enable-method: > contains: > enum: > - brcm,bcm11351-cpu-method > - brcm,bcm23550 > - brcm,bcm-nsp-smp > > then: > required: > - secondary-boot-reg Thanks! That was exactly what I was looking for, it seems to be matching a bit too greedily though: DTC arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml CHECK arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml /home/ff944844/dev/linux/arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml: cpu@0: 'secondary-boot-reg' is a required property /home/ff944844/dev/linux/arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml: cpu@1: 'secondary-boot-reg' is a required property /home/ff944844/dev/linux/arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml: cpu@2: 'secondary-boot-reg' is a required property /home/ff944844/dev/linux/arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml: cpu@3: 'secondary-boot-reg' is a required property DTC arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dt.yaml not sure why though as your example appears correct.
On Mon, Feb 03, 2020 at 09:29:30PM -0800, Florian Fainelli wrote: > > > On 2/3/2020 12:34 AM, Maxime Ripard wrote: > > On Sun, Feb 02, 2020 at 01:18:26PM -0800, Florian Fainelli wrote: > >> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml > >> index c23c24ff7575..6f56a623c1cd 100644 > >> --- a/Documentation/devicetree/bindings/arm/cpus.yaml > >> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml > >> @@ -272,6 +272,22 @@ properties: > >> While optional, it is the preferred way to get access to > >> the cpu-core power-domains. > >> > >> + secondary-boot-reg: > >> + $ref: '/schemas/types.yaml#/definitions/uint32' > >> + description: | > >> + Required for systems that have an "enable-method" property value of > >> + "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". > >> + > >> + This includes the following SoCs: | > >> + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 > >> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 > >> + > >> + The secondary-boot-reg property is a u32 value that specifies the > >> + physical address of the register used to request the ROM holding pen > >> + code release a secondary CPU. The value written to the register is > >> + formed by encoding the target CPU id into the low bits of the > >> + physical start address it should jump to. > >> + > > > > You can make the requirement explicit (and enforced by the schemas) using: > > > > if: > > properties: > > enable-method: > > contains: > > enum: > > - brcm,bcm11351-cpu-method > > - brcm,bcm23550 > > - brcm,bcm-nsp-smp > > > > then: > > required: > > - secondary-boot-reg > > Thanks! That was exactly what I was looking for, it seems to be matching > a bit too greedily though: > > DTC arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml > CHECK arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml > /home/ff944844/dev/linux/arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml: > cpu@0: 'secondary-boot-reg' is a required property > /home/ff944844/dev/linux/arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml: > cpu@1: 'secondary-boot-reg' is a required property > /home/ff944844/dev/linux/arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml: > cpu@2: 'secondary-boot-reg' is a required property > /home/ff944844/dev/linux/arch/arm/boot/dts/bcm2836-rpi-2-b.dt.yaml: > cpu@3: 'secondary-boot-reg' is a required property > DTC arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dt.yaml > > not sure why though as your example appears correct. Yeah, sorry, that's on me :) The nodes that are generating this error are the cpu@[0-3] ones, and they don't have the enable-method property at all. This is because if needs a schema, and will only try to validate the schema under then if the one under if is valid. The one under if contains a list of values for enable-method, but in the case where enable-method is absent, the schema will be valid, and thus the schema under then will be applied. What we actually want to express is "if there's an enable-method property, and that property contains those three values, then you need to have a secondary-boot-reg property." So you need: if: # If the enable-method property contains one of those values properties: enable-method: contains: enum: - brcm,bcm11351-cpu-method - brcm,bcm23550 - brcm,bcm-nsp-smp # and if enable method is present required: - enable-method # Then we need secondary-boot-reg too then: required: - secondary-boot-reg Maxime
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt deleted file mode 100644 index e3f996920403..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt +++ /dev/null @@ -1,36 +0,0 @@ -Broadcom Kona Family CPU Enable Method --------------------------------------- -This binding defines the enable method used for starting secondary -CPUs in the following Broadcom SoCs: - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664 - -The enable method is specified by defining the following required -properties in the "cpu" device tree node: - - enable-method = "brcm,bcm11351-cpu-method"; - - secondary-boot-reg = <...>; - -The secondary-boot-reg property is a u32 value that specifies the -physical address of the register used to request the ROM holding pen -code release a secondary CPU. The value written to the register is -formed by encoding the target CPU id into the low bits of the -physical start address it should jump to. - -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x3500417c>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt deleted file mode 100644 index a3af54c0e404..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt +++ /dev/null @@ -1,36 +0,0 @@ -Broadcom Kona Family CPU Enable Method --------------------------------------- -This binding defines the enable method used for starting secondary -CPUs in the following Broadcom SoCs: - BCM23550 - -The enable method is specified by defining the following required -properties in the "cpu" device tree node: - - enable-method = "brcm,bcm23550"; - - secondary-boot-reg = <...>; - -The secondary-boot-reg property is a u32 value that specifies the -physical address of the register used to request the ROM holding pen -code release a secondary CPU. The value written to the register is -formed by encoding the target CPU id into the low bits of the -physical start address it should jump to. - -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x3500417c>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt deleted file mode 100644 index 677ef9d9f445..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt +++ /dev/null @@ -1,39 +0,0 @@ -Broadcom Northstar Plus SoC CPU Enable Method ---------------------------------------------- -This binding defines the enable method used for starting secondary -CPU in the following Broadcom SoCs: - BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 - -The enable method is specified by defining the following required -properties in the corresponding secondary "cpu" device tree node: - - enable-method = "brcm,bcm-nsp-smp"; - - secondary-boot-reg = <...>; - -The secondary-boot-reg property is a u32 value that specifies the -physical address of the register which should hold the common -entry point for a secondary CPU. This entry is cpu node specific -and should be added per cpu. E.g., in case of NSP (BCM58625) which -is a dual core CPU SoC, this entry should be added to cpu1 node. - - -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - enable-method = "brcm,bcm-nsp-smp"; - secondary-boot-reg = <0xffff042c>; - reg = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index c23c24ff7575..6f56a623c1cd 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -272,6 +272,22 @@ properties: While optional, it is the preferred way to get access to the cpu-core power-domains. + secondary-boot-reg: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Required for systems that have an "enable-method" property value of + "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". + + This includes the following SoCs: | + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 + + The secondary-boot-reg property is a u32 value that specifies the + physical address of the register used to request the ROM holding pen + code release a secondary CPU. The value written to the register is + formed by encoding the target CPU id into the low bits of the + physical start address it should jump to. + required: - device_type - reg
Consolidate and move the 'secondary-boot-reg' property from the 3 existing bindingn document into the main cpus.yaml documentation. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- .../arm/bcm/brcm,bcm11351-cpu-method.txt | 36 ----------------- .../arm/bcm/brcm,bcm23550-cpu-method.txt | 36 ----------------- .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ------------------- .../devicetree/bindings/arm/cpus.yaml | 16 ++++++++ 4 files changed, 16 insertions(+), 111 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt delete mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt delete mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt