| Message ID | 20190925234224.95216-5-john.stultz@linaro.org |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | dwc3: Changes for HiKey960 support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Wed, 2019-09-25 at 23:42 +0000, John Stultz wrote: > Add necessary compatible flag for HiSi's DWC3 so > dwc3-of-simple will probe. > > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > Cc: Felipe Balbi <balbi@kernel.org> > Cc: Andy Shevchenko <andy.shevchenko@gmail.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Yu Chen <chenyu56@huawei.com> > Cc: Matthias Brugger <matthias.bgg@gmail.com> > Cc: Chunfeng Yun <chunfeng.yun@mediatek.com> > Cc: linux-usb@vger.kernel.org > Cc: devicetree@vger.kernel.org > Signed-off-by: John Stultz <john.stultz@linaro.org> > --- > .../devicetree/bindings/usb/hisi,dwc3.txt | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/hisi,dwc3.txt > > diff --git a/Documentation/devicetree/bindings/usb/hisi,dwc3.txt b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt > new file mode 100644 > index 000000000000..dc31b8a3c006 > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt > @@ -0,0 +1,52 @@ > +HiSi SuperSpeed DWC3 USB SoC controller > + > +Required properties: > +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC > +- clocks: A list of phandle + clock-specifier pairs for the > + clocks listed in clock-names > +- clock-names: Should contain the following: > + "clk_usb3phy_ref" Phy reference clk It's not good idea to apply phy's clock in dwc3's node > + "aclk_usb3otg" USB3 OTG aclk > + > +- assigned-clocks: Should be: > + HI3660_ACLK_GATE_USB3OTG > +- assigned-clock-rates: Should be: > + 229Mhz (229000000) for HI3660_ACLK_GATE_USB3OTG > + > +Optional properties: > +- resets: Phandle to reset control that resets core and wrapper. > + > +Required child node: > +A child node must exist to represent the core DWC3 IP block. The name of > +the node is not important. The content of the node is defined in dwc3.txt. > + > +Example device nodes: > + > + usb3: hisi_dwc3 { > + compatible = "hisilicon,hi3660-dwc3"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, > + <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; > + clock-names = "clk_usb3phy_ref", "aclk_usb3otg"; > + > + assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; > + assigned-clock-rates = <229 000 000>; > + resets = <&crg_rst 0x90 8>, > + <&crg_rst 0x90 7>, > + <&crg_rst 0x90 6>, > + <&crg_rst 0x90 5>; > + > + dwc3: dwc3@ff100000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0xff100000 0x0 0x100000>; > + interrupts = <0 159 4>, <0 161 4>; > + phys = <&usb_phy>; > + phy-names = "usb3-phy"; > + dr_mode = "otg"; > + > + ... > + }; > + };
On Wed, Sep 25, 2019 at 6:34 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote: > On Wed, 2019-09-25 at 23:42 +0000, John Stultz wrote: > > +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt > > @@ -0,0 +1,52 @@ > > +HiSi SuperSpeed DWC3 USB SoC controller > > + > > +Required properties: > > +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC > > +- clocks: A list of phandle + clock-specifier pairs for the > > + clocks listed in clock-names > > +- clock-names: Should contain the following: > > + "clk_usb3phy_ref" Phy reference clk > It's not good idea to apply phy's clock in dwc3's node Hey! Thanks for taking a look at this! So first, my apologies, I'm not the driver author and I don't have any real specs on the hardware other then what's in the source tree I'm working on. Not the ideal person to be documenting the binding, but I realized we still needed some binding documentation (although a few other dwc-of-simple compat entries are undocumented), so this is my rough stab at it. :/ Given the name clk_usb3phy_ref I'm assuming its a phy reference clock, but I honestly don't know if I'm getting that wrong. It all seems to be leveraging the fact that the dwc-of-simple driver batch enables and disables all the clocks w/o really looking at the names. Do you have a recommendation for what would be best here? I suspect it's necessary to enable/disable the clk in a similar path(though I'm unfortunately traveling this week so I can't validate that). Do I try to move the clk_usb3phy_ref clock enable/disable handling to somewhere else? thanks -john
On Wed, 2019-09-25 at 21:06 -0700, John Stultz wrote: > On Wed, Sep 25, 2019 at 6:34 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote: > > On Wed, 2019-09-25 at 23:42 +0000, John Stultz wrote: > > > +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt > > > @@ -0,0 +1,52 @@ > > > +HiSi SuperSpeed DWC3 USB SoC controller > > > + > > > +Required properties: > > > +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC > > > +- clocks: A list of phandle + clock-specifier pairs for the > > > + clocks listed in clock-names > > > +- clock-names: Should contain the following: > > > + "clk_usb3phy_ref" Phy reference clk > > It's not good idea to apply phy's clock in dwc3's node > > Hey! Thanks for taking a look at this! > > So first, my apologies, I'm not the driver author and I don't have any > real specs on the hardware other then what's in the source tree I'm > working on. Not the ideal person to be documenting the binding, but I > realized we still needed some binding documentation (although a few > other dwc-of-simple compat entries are undocumented), so this is my > rough stab at it. :/ > > Given the name clk_usb3phy_ref I'm assuming its a phy reference clock, > but I honestly don't know if I'm getting that wrong. It all seems to > be leveraging the fact that the dwc-of-simple driver batch enables and > disables all the clocks w/o really looking at the names. > > Do you have a recommendation for what would be best here? I suspect > it's necessary to enable/disable the clk in a similar path(though I'm > unfortunately traveling this week so I can't validate that). Do I try > to move the clk_usb3phy_ref clock enable/disable handling to somewhere > else? If it's phy clock, we should enable/disable it in phy driver, maybe we'd better ask for help from Yu Chen > > thanks > -john
On Wed, Sep 25, 2019 at 11:42 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote: > On Wed, 2019-09-25 at 21:06 -0700, John Stultz wrote: > > On Wed, Sep 25, 2019 at 6:34 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote: > > > On Wed, 2019-09-25 at 23:42 +0000, John Stultz wrote: > > > > +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt > > > > @@ -0,0 +1,52 @@ > > > > +HiSi SuperSpeed DWC3 USB SoC controller > > > > + > > > > +Required properties: > > > > +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC > > > > +- clocks: A list of phandle + clock-specifier pairs for the > > > > + clocks listed in clock-names > > > > +- clock-names: Should contain the following: > > > > + "clk_usb3phy_ref" Phy reference clk > > > It's not good idea to apply phy's clock in dwc3's node ... > > Given the name clk_usb3phy_ref I'm assuming its a phy reference clock, > > but I honestly don't know if I'm getting that wrong. It all seems to > > be leveraging the fact that the dwc-of-simple driver batch enables and > > disables all the clocks w/o really looking at the names. > > ... > If it's phy clock, we should enable/disable it in phy driver, maybe we'd > better ask for help from Yu Chen So I've been looking around the existing code and I'm not sure how we got to clk_usb3phy_ref here. Really it is the HI3660_CLK_ABB_USB, who's name is "clk_abb_usb" and who's parent is "clk_gate_usb_tcxo_en" So I'm thinking just specifying clk_abb_usb is more accurate here? Does that sound reasonable? thanks -john
diff --git a/Documentation/devicetree/bindings/usb/hisi,dwc3.txt b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt new file mode 100644 index 000000000000..dc31b8a3c006 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt @@ -0,0 +1,52 @@ +HiSi SuperSpeed DWC3 USB SoC controller + +Required properties: +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Should contain the following: + "clk_usb3phy_ref" Phy reference clk + "aclk_usb3otg" USB3 OTG aclk + +- assigned-clocks: Should be: + HI3660_ACLK_GATE_USB3OTG +- assigned-clock-rates: Should be: + 229Mhz (229000000) for HI3660_ACLK_GATE_USB3OTG + +Optional properties: +- resets: Phandle to reset control that resets core and wrapper. + +Required child node: +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +Example device nodes: + + usb3: hisi_dwc3 { + compatible = "hisilicon,hi3660-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, + <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + clock-names = "clk_usb3phy_ref", "aclk_usb3otg"; + + assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + assigned-clock-rates = <229 000 000>; + resets = <&crg_rst 0x90 8>, + <&crg_rst 0x90 7>, + <&crg_rst 0x90 6>, + <&crg_rst 0x90 5>; + + dwc3: dwc3@ff100000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff100000 0x0 0x100000>; + interrupts = <0 159 4>, <0 161 4>; + phys = <&usb_phy>; + phy-names = "usb3-phy"; + dr_mode = "otg"; + + ... + }; + };
Add necessary compatible flag for HiSi's DWC3 so dwc3-of-simple will probe. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Felipe Balbi <balbi@kernel.org> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Yu Chen <chenyu56@huawei.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Chunfeng Yun <chunfeng.yun@mediatek.com> Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz <john.stultz@linaro.org> --- .../devicetree/bindings/usb/hisi,dwc3.txt | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/hisi,dwc3.txt