diff mbox series

[v2,4/9] dt-bindings: power: Add rpm power domain bindings for qcs404

Message ID 20190324175007.29040-5-sibis@codeaurora.org
State Superseded, archived
Headers show
Series RPMPD for QCS404 and MSM8998 | expand

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Commit Message

Sibi Sankar March 24, 2019, 5:50 p.m. UTC
From: Bjorn Andersson <bjorn.andersson@linaro.org>

Add RPM Power domain bindings for the qcs404 family of SoC

[sibis: Add supported rpmpd states for qcs404]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 .../devicetree/bindings/power/qcom,rpmpd.txt  |  1 +
 include/dt-bindings/power/qcom-rpmpd.h        | 22 +++++++++++++++++++
 2 files changed, 23 insertions(+)

Comments

Rajendra Nayak March 25, 2019, 4:21 a.m. UTC | #1
On 3/24/2019 11:20 PM, Sibi Sankar wrote:
> From: Bjorn Andersson <bjorn.andersson@linaro.org>
> 
> Add RPM Power domain bindings for the qcs404 family of SoC
> 
> [sibis: Add supported rpmpd states for qcs404]
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>

SoB ordering seems wrong.

> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>   .../devicetree/bindings/power/qcom,rpmpd.txt  |  1 +
>   include/dt-bindings/power/qcom-rpmpd.h        | 22 +++++++++++++++++++
>   2 files changed, 23 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt
> index 980e5413d18f..172ccf940c5c 100644
> --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt
> +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt
> @@ -6,6 +6,7 @@ which then translates it into a corresponding voltage on a rail
>   Required Properties:
>    - compatible: Should be one of the following
>   	* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC
> +	* qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC
>   	* qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC
>    - #power-domain-cells: number of cells in Power domain specifier
>   	must be 1.
> diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
> index 87d9c6611682..450378662944 100644
> --- a/include/dt-bindings/power/qcom-rpmpd.h
> +++ b/include/dt-bindings/power/qcom-rpmpd.h
> @@ -36,4 +36,26 @@
>   #define MSM8996_VDDSSCX		5
>   #define MSM8996_VDDSSCX_VFC	6
>   
> +/* QCS404 Power Domains */
> +#define QCS404_VDDMX		0
> +#define QCS404_VDDMX_AO		1
> +#define QCS404_VDDMX_VFL	2
> +#define QCS404_LPICX		3
> +#define QCS404_LPICX_VFL	4
> +#define QCS404_LPIMX		5
> +#define QCS404_LPIMX_VFL	6
> +
> +/* RPM SMD Power Domain performance levels */

so unlike in the sdm845 case where we map these levels to
(contiguous) corners before passing it over to rpm, we seem
to pass these as-is to rpm, right?

Does this work if the user passes some value which does not
really map to a level defined here?
For instance if value passed is 17 for instance do we fall back to
16?
  
> +#define RPM_SMD_LEVEL_RETENTION       16
> +#define RPM_SMD_LEVEL_RETENTION_PLUS  32
> +#define RPM_SMD_LEVEL_MIN_SVS         48
> +#define RPM_SMD_LEVEL_LOW_SVS         64
> +#define RPM_SMD_LEVEL_SVS             128
> +#define RPM_SMD_LEVEL_SVS_PLUS        192
> +#define RPM_SMD_LEVEL_NOM             256
> +#define RPM_SMD_LEVEL_NOM_PLUS        320
> +#define RPM_SMD_LEVEL_TURBO           384
> +#define RPM_SMD_LEVEL_TURBO_NO_CPR    416
> +#define RPM_SMD_LEVEL_BINNING         512
> +
>   #endif
>
Sibi Sankar March 27, 2019, 1:25 p.m. UTC | #2
On 2019-03-25 09:51, Rajendra Nayak wrote:
> On 3/24/2019 11:20 PM, Sibi Sankar wrote:
>> From: Bjorn Andersson <bjorn.andersson@linaro.org>
>> 
>> Add RPM Power domain bindings for the qcs404 family of SoC
>> 
>> [sibis: Add supported rpmpd states for qcs404]
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> 
> SoB ordering seems wrong.

will re-order them in v3

> 
>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> ---
>>   .../devicetree/bindings/power/qcom,rpmpd.txt  |  1 +
>>   include/dt-bindings/power/qcom-rpmpd.h        | 22 
>> +++++++++++++++++++
>>   2 files changed, 23 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt 
>> b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt
>> index 980e5413d18f..172ccf940c5c 100644
>> --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt
>> +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt
>> @@ -6,6 +6,7 @@ which then translates it into a corresponding voltage 
>> on a rail
>>   Required Properties:
>>    - compatible: Should be one of the following
>>   	* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of 
>> SoC
>> +	* qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC
>>   	* qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of 
>> SoC
>>    - #power-domain-cells: number of cells in Power domain specifier
>>   	must be 1.
>> diff --git a/include/dt-bindings/power/qcom-rpmpd.h 
>> b/include/dt-bindings/power/qcom-rpmpd.h
>> index 87d9c6611682..450378662944 100644
>> --- a/include/dt-bindings/power/qcom-rpmpd.h
>> +++ b/include/dt-bindings/power/qcom-rpmpd.h
>> @@ -36,4 +36,26 @@
>>   #define MSM8996_VDDSSCX		5
>>   #define MSM8996_VDDSSCX_VFC	6
>>   +/* QCS404 Power Domains */
>> +#define QCS404_VDDMX		0
>> +#define QCS404_VDDMX_AO		1
>> +#define QCS404_VDDMX_VFL	2
>> +#define QCS404_LPICX		3
>> +#define QCS404_LPICX_VFL	4
>> +#define QCS404_LPIMX		5
>> +#define QCS404_LPIMX_VFL	6
>> +
>> +/* RPM SMD Power Domain performance levels */
> 
> so unlike in the sdm845 case where we map these levels to
> (contiguous) corners before passing it over to rpm, we seem
> to pass these as-is to rpm, right?
> 
> Does this work if the user passes some value which does not
> really map to a level defined here?
> For instance if value passed is 17 for instance do we fall back to
> 16?

The rpm firmware will ensure that a ceil operation
is performed on any requested level which does not
map to a pre-defined level. I did try to do the
same in kernel however since the opp-levels are not
inserted in ascending order while populating the
opp-table for rpmpd, it becomes difficult to get
ceil/floor levels from the opp-table with minimal
changes.


> 
>> +#define RPM_SMD_LEVEL_RETENTION       16
>> +#define RPM_SMD_LEVEL_RETENTION_PLUS  32
>> +#define RPM_SMD_LEVEL_MIN_SVS         48
>> +#define RPM_SMD_LEVEL_LOW_SVS         64
>> +#define RPM_SMD_LEVEL_SVS             128
>> +#define RPM_SMD_LEVEL_SVS_PLUS        192
>> +#define RPM_SMD_LEVEL_NOM             256
>> +#define RPM_SMD_LEVEL_NOM_PLUS        320
>> +#define RPM_SMD_LEVEL_TURBO           384
>> +#define RPM_SMD_LEVEL_TURBO_NO_CPR    416
>> +#define RPM_SMD_LEVEL_BINNING         512
>> +
>>   #endif
>>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt
index 980e5413d18f..172ccf940c5c 100644
--- a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt
+++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt
@@ -6,6 +6,7 @@  which then translates it into a corresponding voltage on a rail
 Required Properties:
  - compatible: Should be one of the following
 	* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC
+	* qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC
 	* qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC
  - #power-domain-cells: number of cells in Power domain specifier
 	must be 1.
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index 87d9c6611682..450378662944 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -36,4 +36,26 @@ 
 #define MSM8996_VDDSSCX		5
 #define MSM8996_VDDSSCX_VFC	6
 
+/* QCS404 Power Domains */
+#define QCS404_VDDMX		0
+#define QCS404_VDDMX_AO		1
+#define QCS404_VDDMX_VFL	2
+#define QCS404_LPICX		3
+#define QCS404_LPICX_VFL	4
+#define QCS404_LPIMX		5
+#define QCS404_LPIMX_VFL	6
+
+/* RPM SMD Power Domain performance levels */
+#define RPM_SMD_LEVEL_RETENTION       16
+#define RPM_SMD_LEVEL_RETENTION_PLUS  32
+#define RPM_SMD_LEVEL_MIN_SVS         48
+#define RPM_SMD_LEVEL_LOW_SVS         64
+#define RPM_SMD_LEVEL_SVS             128
+#define RPM_SMD_LEVEL_SVS_PLUS        192
+#define RPM_SMD_LEVEL_NOM             256
+#define RPM_SMD_LEVEL_NOM_PLUS        320
+#define RPM_SMD_LEVEL_TURBO           384
+#define RPM_SMD_LEVEL_TURBO_NO_CPR    416
+#define RPM_SMD_LEVEL_BINNING         512
+
 #endif