From patchwork Fri Nov 2 21:45:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 992559 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="HIQwPujD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42mwcQ0yZhzB4b5 for ; Sat, 3 Nov 2018 08:45:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727780AbeKCGyp (ORCPT ); Sat, 3 Nov 2018 02:54:45 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:37757 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726083AbeKCGyp (ORCPT ); Sat, 3 Nov 2018 02:54:45 -0400 Received: by mail-pl1-f194.google.com with SMTP id p6-v6so1566944pll.4 for ; Fri, 02 Nov 2018 14:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/218tbqYfFYsBPGuhJ4jRp/KJJyqAyXjQYUAJueIJAw=; b=HIQwPujDGHbE0eemGaXVPA4oXY2ITV39RDp31VfruMJpV/Gb1Box6rFLnGt5Us3vTl nJXX5nV0RT2S+lvR/2JOqcNXKIgEWLSHPUU9HsmR936AIfDqmryOd4n/nFvR7On/pvsd B/EGLKM8wtcQlK01dqtvAO3LWbWANknLOkX/c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/218tbqYfFYsBPGuhJ4jRp/KJJyqAyXjQYUAJueIJAw=; b=kc0BCy+xWkCtaWDbiQd9djIVtRVLySRIscc+c6M/BtA4/qqcfFTHtqRQaUXhPVzgvM S0GaKWYSH+k/2wKjlGaKoLzOhWNBRo0vb9jwcsabtiLK42nFWOmnEjoITbeE4/tY2gLV mewiEuO4+U6lIiei6L78cc5X+KeGEQKD9XZ7b/QTbbpBHfFnJ26viMnCp8qZ3nxFB8tT zrhW4O5+PJFN9zigKqJCOMiP9l/cFlf39OdcqHqGfbuzW3rvT2iK/lbXglXV0A2FGeJC BipqjXamHSiwRP+tRwr1dxGvHCye2gJXH+bwcpU9+7ItmiiO+23hDITU00VpUBbbFjQ9 a7Mw== X-Gm-Message-State: AGRZ1gIv536pVnCEHmtjjoRWnFdpTc1VFfUSC37DssHe7n6hsq+KxirN FVPTLXYFfJxUusp2T/Aj90lM2g== X-Google-Smtp-Source: AJdET5dfIGnnDzIpt0LuWmctxVcZrO+0fVanfeejho0Wf24FbzURFwVe7dYwqoTJsMusQuoq19tr4A== X-Received: by 2002:a17:902:a50e:: with SMTP id s14-v6mr13316568plq.78.1541195154784; Fri, 02 Nov 2018 14:45:54 -0700 (PDT) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:b6af:f85:ed6c:ac6a]) by smtp.gmail.com with ESMTPSA id q25-v6sm58332871pfk.154.2018.11.02.14.45.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Nov 2018 14:45:54 -0700 (PDT) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland Cc: Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH 1/2] dt-bindings: msm/dsi: Add ref clock for 10nm PHY Date: Fri, 2 Nov 2018 14:45:33 -0700 Message-Id: <20181102214534.184593-1-mka@chromium.org> X-Mailer: git-send-email 2.19.1.930.g4563a0d9d0-goog MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow the 10nm PHY driver to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke --- Documentation/devicetree/bindings/display/msm/dsi.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..d0d2046ceff69 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -105,6 +105,10 @@ Required properties: - power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: + For 10nm PHY: + * "iface" + * "ref" + For other PHYs: * "iface" For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node