From patchwork Sat Oct 20 13:50:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 987200 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="RdWIrKup"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42ckhH4DRMz9sDb for ; Sun, 21 Oct 2018 00:50:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727539AbeJTWBO (ORCPT ); Sat, 20 Oct 2018 18:01:14 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:45783 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727544AbeJTWBO (ORCPT ); Sat, 20 Oct 2018 18:01:14 -0400 Received: by mail-wr1-f66.google.com with SMTP id f17-v6so8457066wrs.12 for ; Sat, 20 Oct 2018 06:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TwLCHpP8kf+4rr/NbIN453XbTBZTe4XodmQVrexotJY=; b=RdWIrKupHcDvm18Sfo9zS/lrKGcwiUvge3qibXzdVmaed+ACU+7HnBHQMPlvut8W5J FgOsCoi5GXfb2mujHsZ/AVCommDwAPmYQAOFpg/gajevBp4NHPqDjKmKKdlQ6WXPKahy Azs+icTGaoh5BQ3NDLvsUBoNR05C/khgIIYl62Hg5tVHcD+t3sCZEGKBGEBoOVNDFyRp AU72yPT+gMZak0Q/frX18AUp3iVrOh7COPpxh0o2X2qwjtryQ45M14k/UmnR0l4TCpdX OPgf/MmBaKcTStXOQBNp17zc6nEHSBB+Kkcbsay2SPd5y9WYUThXFNgJZ2ljGpjau9fb +VuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TwLCHpP8kf+4rr/NbIN453XbTBZTe4XodmQVrexotJY=; b=pS68L/se41VoiI3TfWPs7p9tX/FfGXXWMJ7E1Efqvf+9Gb9NVOEVY/MYWdrwPEyiHQ 0Jt99hqMbwg9p/PRSRMDmD1QjR1FFlSo7HDzUe3fiVKS7yh6c9xroluN2mRnFfpa6AOG 6lnoy08TUSdA1FrOtJr+hOUGYggqMLSAWWuiqafXg9FNSwedc4q7c1fl8os0pNYw8ezQ e/nNXQ+ny1GLZ21aA0ElrWmgPv1/cwseoVxLw+b7dXHcE4wv+UN9nW8E3mtTgAYMmAYl uY5u2IKeHw7rBtXkXbJTImMz01WIFGcADcoXGKGUKJ+9s+oHVrJR0Wnk+QdjqXpVbHNm hpow== X-Gm-Message-State: ABuFfoj13807bGz+4NSa/XkDeaA1jVndyeEMoKxKbItiROnZf0W0DMOb 9kstUu7LBqiLQ/0ViLqntPLNQA== X-Google-Smtp-Source: ACcGV61PlikZUj7Qbw+Lc/0wkLSwO/nJIyd8fEDd9dpzZWi3QLt9RKDFst4+6CBC5bnhigN2ytGl3w== X-Received: by 2002:adf:ecc9:: with SMTP id s9-v6mr36018146wro.142.1540043439647; Sat, 20 Oct 2018 06:50:39 -0700 (PDT) Received: from viisi.sifive.com ([37.152.39.96]) by smtp.gmail.com with ESMTPSA id o4-v6sm16906615wrj.45.2018.10.20.06.50.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Oct 2018 06:50:39 -0700 (PDT) From: Paul Walmsley To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Paul Walmsley , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Palmer Dabbelt , Megan Wachs , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Paul Walmsley Subject: [PATCH v2 2/3] dt-bindings: clk: add documentation for the SiFive PRCI driver Date: Sat, 20 Oct 2018 06:50:23 -0700 Message-Id: <20181020135024.28573-3-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181020135024.28573-1-paul.walmsley@sifive.com> References: <20181020135024.28573-1-paul.walmsley@sifive.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding documentation for the Linux driver for the SiFive PRCI clock & reset control IP block, as found on the SiFive FU540 chip. Cc: Michael Turquette Cc: Stephen Boyd Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Cc: Megan Wachs Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley --- v2: remove out-of-date example, add documentation for the compatible string and for the required PCB clock nodes .../bindings/clock/sifive/fu540-prci.txt | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt new file mode 100644 index 000000000000..d7c1e83fa5ed --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt @@ -0,0 +1,43 @@ +SiFive FU540 PRCI bindings + +On the FU540 family of SoCs, most system-wide clock and reset integration +is via the PRCI IP block. + +Required properties: +- compatible: Should be "sifive,-prci". As of the time this + file was written, only one value is supported: + "sifive,fu540-c000-prci0" +- reg: Should describe the PRCI's register target physical address region +- clocks: Should point to the hfclk device tree node and the rtcclk + device tree node. The RTC clock here is not a time-of-day clock, + but is instead a high-stability clock source for system timers + and cycle counters. +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock via the clock ID +macros defined in include/linux/clk/sifive-fu540-prci.h. These macros +begin with PRCI_CLK_. + +The hfclk and rtcclk nodes are required, and represent physical +crystals or resonators located on the PCB. + +Examples: + +hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; +}; +rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; +}; +prci0: prci@10000000 { + compatible = "sifive,fu540-c000-prci0"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; +};