| Message ID | 20180919210219.21921-1-zajec5@gmail.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | [1/2] dt-bindings: pinctrl: document Broadcom Northstar pin mux controller | expand |
On 09/19/2018 02:02 PM, Rafał Miłecki wrote: > From: Rafał Miłecki <rafal@milecki.pl> > > Northstar has mux controller just like Northstar Plus and Northstar2. > It's a bit different though (different registers & pins) so it requires > its own binding. > > It's needed to allow other block bindings specify required mux setup. > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > --- > .../devicetree/bindings/pinctrl/brcm,ns-pinmux.txt | 29 ++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt > > diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt > new file mode 100644 > index 000000000000..0e913721ae9e > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt > @@ -0,0 +1,29 @@ > +Broadcom Northstar pins mux controller > + > +Some of Northstar SoCs's pins can be used for various purposes thanks to the mux > +controller. This binding allows describing mux controller and listing available > +functions. They can be referenced later by other bindings to let system > +configure controller correctly. > + > +Required properties: > +- compatible: brcm,ns-pinmux > +- reg: iomem address range of CRU (Central Resource Unit) pin registers > +- reg-names: "cru_pins_control" - the only needed & supported reg right now Technically the register range that you cover is named CRU_GPIO_CONTROLx with x being in [0-8]. Other than that: Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
On 09/19/2018 02:02 PM, Rafał Miłecki wrote: > From: Rafał Miłecki <rafal@milecki.pl> > > This driver provides support for Northstar mux controller. It differs > from Northstar Plus one so a new binding and driver were needed. > > Right now it includes support for SPI pins only which is caused by a > lack of access to Broadcom's datasheet. SPI pins info was extracted from > the Broadcom's SDK. Once more pins are discovered they can be added to > the driver without breaking any existing setups. > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > --- [snip] > +static const struct pinctrl_pin_desc ns_pinctrl_pins[] = { > + { 0, "spi_clk" }, > + { 1, "spi_ss" }, > + { 2, "spi_mosi" }, > + { 3, "spi_miso" }, > +}; In case you are interested, here are the additional functions: 4: i2c_scl 5: i2c_sda 6: mdc 7: mdio 8: pwm0 9: pwm1 10: pwm2 11: pwm3 12: uart1_rx 13: uart1_tx 14: uart1_cts 15: uart1_rts On BCM53012: 16: uart2_rx 17: uart2_tx 22: sdio_card_power_ctl 23: sdio_en_1p8 On BCM53013: 21: 25Mhz crystal output for I2S Not an expert on pinctrl drivers, but it looks reasonable to me.
On Wed, 19 Sep 2018 at 23:22, Florian Fainelli <f.fainelli@gmail.com> wrote: > On 09/19/2018 02:02 PM, Rafał Miłecki wrote: > > From: Rafał Miłecki <rafal@milecki.pl> > > > > Northstar has mux controller just like Northstar Plus and Northstar2. > > It's a bit different though (different registers & pins) so it requires > > its own binding. > > > > It's needed to allow other block bindings specify required mux setup. > > > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > > --- > > .../devicetree/bindings/pinctrl/brcm,ns-pinmux.txt | 29 ++++++++++++++++++++++ > > 1 file changed, 29 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt > > new file mode 100644 > > index 000000000000..0e913721ae9e > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt > > @@ -0,0 +1,29 @@ > > +Broadcom Northstar pins mux controller > > + > > +Some of Northstar SoCs's pins can be used for various purposes thanks to the mux > > +controller. This binding allows describing mux controller and listing available > > +functions. They can be referenced later by other bindings to let system > > +configure controller correctly. > > + > > +Required properties: > > +- compatible: brcm,ns-pinmux > > +- reg: iomem address range of CRU (Central Resource Unit) pin registers > > +- reg-names: "cru_pins_control" - the only needed & supported reg right now > > Technically the register range that you cover is named CRU_GPIO_CONTROLx > with x being in [0-8]. Thanks! Do you think reg-names: "cru_gpio_controls" will be fine? Or should I keep it singular like: reg-names: "cru_gpio_control" ?
On 9/19/18 11:45 PM, Florian Fainelli wrote: > On 09/19/2018 02:02 PM, Rafał Miłecki wrote: >> From: Rafał Miłecki <rafal@milecki.pl> >> >> This driver provides support for Northstar mux controller. It differs >> from Northstar Plus one so a new binding and driver were needed. >> >> Right now it includes support for SPI pins only which is caused by a >> lack of access to Broadcom's datasheet. SPI pins info was extracted from >> the Broadcom's SDK. Once more pins are discovered they can be added to >> the driver without breaking any existing setups. >> >> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> >> --- > > [snip] > >> +static const struct pinctrl_pin_desc ns_pinctrl_pins[] = { >> + { 0, "spi_clk" }, >> + { 1, "spi_ss" }, >> + { 2, "spi_mosi" }, >> + { 3, "spi_miso" }, >> +}; > > In case you are interested, here are the additional functions: > > 4: i2c_scl > 5: i2c_sda > > 6: mdc > 7: mdio > > 8: pwm0 > 9: pwm1 > 10: pwm2 > 11: pwm3 > > 12: uart1_rx > 13: uart1_tx > 14: uart1_cts > 15: uart1_rts > > On BCM53012: > > 16: uart2_rx > 17: uart2_tx > 22: sdio_card_power_ctl > 23: sdio_en_1p8 > > On BCM53013: > > 21: 25Mhz crystal output for I2S I believe what you provided are name of bits in the cru_genpll_control0 register. FWIW that info would be part of ns_pins_data rather than ns_pinctrl_pins. I was aware of most of them thanks to analyzing bcm5301x_dmu.c from the SDK but some are still new to me, so thanks for that! What I'm really missing are SoC pin numbers for all above. E.g. what hardware pin number is used for the uart2_rx? Or sdio_card_power_ctl? And all the other ones. If you could provide that info it'd be extremely helpful. *** If you take a look at pinctrl-nsp-mux.c, you'll see that there isn't 1:1 mapping used on Broadcom platforms. E.g. Northstar Plus has SoC pins 4 and 5 used for I2C: i2c_pins[] = {4, 5}; but they are controlled by BIT(3) and BIT(4) of the BASE0 register: NSP_PIN_GROUP(i2c, NSP_MUX_BASE0, 3, 0x03, 0x00), (0x03 << 3) Another NSP example: SoC pins 16 and 17 are used for UART2: uart2_pins[] = {16, 17}; but they are controlled by BIT(15) and BIT(16) of the BASE0 register: NSP_PIN_GROUP(uart2, NSP_MUX_BASE0, 15, 0x03, 0x00), (0x03 << 15) Of course, some pins map 1:1, e.g. pin 26 for LED of switch port 5: switch_p05_led0_pins[] = {26}; maps nicely to BIT(26) of the BASE0 register: NSP_PIN_GROUP(switch_p05_led0, NSP_MUX_BASE0, 26, 0x01, 0x01), (0x01 << 26) but it clearly isn't a rule.
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt new file mode 100644 index 000000000000..0e913721ae9e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt @@ -0,0 +1,29 @@ +Broadcom Northstar pins mux controller + +Some of Northstar SoCs's pins can be used for various purposes thanks to the mux +controller. This binding allows describing mux controller and listing available +functions. They can be referenced later by other bindings to let system +configure controller correctly. + +Required properties: +- compatible: brcm,ns-pinmux +- reg: iomem address range of CRU (Central Resource Unit) pin registers +- reg-names: "cru_pins_control" - the only needed & supported reg right now + +List of supported functions and their groups: +- "spi": "spi_grp" + +For documentation of subnodes see: +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example: + pinctrl@1800c1c0 { + compatible = "brcm,ns-pinmux"; + reg = <0x1800c1c0 0x24>; + reg-names = "cru_pins_control"; + + spi { + function = "spi"; + groups = "spi_grp"; + }; + };