From patchwork Sun Sep 9 20:16:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 967808 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hauke-m.de Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 427jCH30gjz9s4V for ; Mon, 10 Sep 2018 06:17:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726775AbeIJBIN (ORCPT ); Sun, 9 Sep 2018 21:08:13 -0400 Received: from mx2.mailbox.org ([80.241.60.215]:21042 "EHLO mx2.mailbox.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726725AbeIJBIN (ORCPT ); Sun, 9 Sep 2018 21:08:13 -0400 Received: from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx2.mailbox.org (Postfix) with ESMTPS id BD49B42068; Sun, 9 Sep 2018 22:17:22 +0200 (CEST) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp1.mailbox.org ([80.241.60.240]) by gerste.heinlein-support.de (gerste.heinlein-support.de [91.198.250.173]) (amavisd-new, port 10030) with ESMTP id QEalBPYW7qHh; Sun, 9 Sep 2018 22:17:21 +0200 (CEST) From: Hauke Mehrtens To: davem@davemloft.net Cc: netdev@vger.kernel.org, andrew@lunn.ch, vivien.didelot@savoirfairelinux.com, f.fainelli@gmail.com, john@phrozen.org, linux-mips@linux-mips.org, dev@kresin.me, hauke.mehrtens@intel.com, devicetree@vger.kernel.org, Hauke Mehrtens Subject: [PATCH v3 net-next 3/6] dt-bindings: net: Add lantiq, xrx200-net DT bindings Date: Sun, 9 Sep 2018 22:16:44 +0200 Message-Id: <20180909201647.32727-4-hauke@hauke-m.de> In-Reply-To: <20180909201647.32727-1-hauke@hauke-m.de> References: <20180909201647.32727-1-hauke@hauke-m.de> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the binding for the PMAC core between the CPU and the GSWIP switch found on the xrx200 / VR9 Lantiq / Intel SoC. Signed-off-by: Hauke Mehrtens Cc: devicetree@vger.kernel.org --- .../devicetree/bindings/net/lantiq,xrx200-net.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt diff --git a/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt new file mode 100644 index 000000000000..8a2fe5200cdc --- /dev/null +++ b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt @@ -0,0 +1,21 @@ +Lantiq xRX200 GSWIP PMAC Ethernet driver +================================== + +Required properties: + +- compatible : "lantiq,xrx200-net" for the PMAC of the embedded + : GSWIP in the xXR200 +- reg : memory range of the PMAC core inside of the GSWIP core +- interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for + : the TX interrupt and "rx" for the RX interrupt. + +Example: + +eth0: eth@E10B308 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = <0xE10B308 0x30>; + interrupts = <73>, <72>; + interrupt-names = "tx", "rx"; +};