From patchwork Fri May 11 22:02:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 912230 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kXdun+6f"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40jPHK1Bmlz9s19 for ; Sat, 12 May 2018 08:03:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752017AbeEKWDX (ORCPT ); Fri, 11 May 2018 18:03:23 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:40171 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751904AbeEKWDG (ORCPT ); Fri, 11 May 2018 18:03:06 -0400 Received: by mail-pf0-f194.google.com with SMTP id f189-v6so3309315pfa.7; Fri, 11 May 2018 15:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9GG6R/Yg6y+F5KMKD6PeCoumED2ZkuLEgKXurPvTF8I=; b=kXdun+6fDTiO6pSylAhJcS3PeL4b2oG82iMIid0hl42Er7unE/xWZ5t85iKC8NoknV PYNrw4fWvUmUZu0kVefMSWWtdqBRFOKKzXv5M+q2KT6LtfbGuVp98UwVcUrHDqXu3TH+ etJ9xwCnpvtc8a+sa8tTczopcQ+N4yL75GS50ybkAEHCOo0jrrQN5gqO2+yfwSaxuDOi koYwdDbeJgEeIiHfIPrAx4HN0hg608+w9U6xNz4Z7LLXxvZyqBs93q5fZPLjezIcAPnx McT772J2MliuIzOvda8sNEQTO3Kn5au26nrCQ2sjC20A5AHmoS/PhwbehaXRHktSH0qE FTkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9GG6R/Yg6y+F5KMKD6PeCoumED2ZkuLEgKXurPvTF8I=; b=MfVwOAuObLUImeNsEL/bm1mfn2TfdwZAG6dJLkOSFdHxmzNHx5LDwC++UwpKjqnnPg te9GbmDFyIv+0ydqzvSinC2C4JGwEVWHeHlXAIGmENgR/P9OpkJAku3qDcSqHNHFwSpq 3o0Y1Mo3qXEqcS8f273RkJzmYJAvH4o/47z9QT1mzDU1th61GMQa+q59JyvQ5W1zTNuG te10GHiO/31R2bQhRDEifMYVJknAyUJqvKmRIn1HuTFE75OX66MfT0whE10It/LJiqV6 lYdeQGEas7US9afg6vTJCmpMhSB2EFWzH4+dnTsbWz6cbbcU+dlJqA6NpKlmrA4DAzHV xpLg== X-Gm-Message-State: ALKqPwf57LltiGGzaubBRSsQcCDldkjXBuD54GIfE8Py79kqS9/nf7vm 5psEASTP2f7hQ3JNaraPQQ10LDZK X-Google-Smtp-Source: AB8JxZrmQn/YgpUOIU3EpCFp0jr4xo0G3byeLzfwnYHDaEPwsFGp/7jHv6DVabdGDbSbgs4ZQEaDfg== X-Received: by 2002:a62:9b8d:: with SMTP id e13-v6mr515413pfk.157.1526076185999; Fri, 11 May 2018 15:03:05 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.250]) by smtp.gmail.com with ESMTPSA id r8-v6sm6311637pgn.2.2018.05.11.15.03.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 May 2018 15:03:05 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Cc: Florian Fainelli , Rob Herring , Mark Rutland , Brian Norris , Gregory Fong , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Doug Berger , Justin Chen , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/2] soc: bcm: brcmstb: Add missing DDR MEMC compatible strings Date: Fri, 11 May 2018 15:02:42 -0700 Message-Id: <20180511220242.837-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180511220242.837-1-f.fainelli@gmail.com> References: <20180511220242.837-1-f.fainelli@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We would not be matching the following chip/compatible strings combinations, which would lead to not setting the warm boot flag correctly, fix that: 7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1 7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3 7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1 The B2.1 core (which is in 7260 A0 and B0) doesn't have the SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor does it have the warm boot flag re-definition on entry. Those changes were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3 entry method for these specific chips. Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") Signed-off-by: Florian Fainelli Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 3 +++ drivers/soc/bcm/brcmstb/pm/pm-arm.c | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index fb762059e68e..104cc9b41df4 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -189,8 +189,11 @@ Power-Down (SRPD), among other things. Required properties: - compatible : should contain one of these + "brcm,brcmstb-memc-ddr-rev-b.2.1" "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr-rev-b.2.3" "brcm,brcmstb-memc-ddr-rev-b.3.0" + "brcm,brcmstb-memc-ddr-rev-b.3.1" "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index ade724677238..a5577dd5eb08 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -627,14 +627,26 @@ static const struct of_device_id ddr_shimphy_dt_ids[] = { }; static const struct of_device_id brcmstb_memc_of_match[] = { + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1", + .data = &ddr_seq, + }, { .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr", .data = &ddr_seq,