From patchwork Thu Mar 15 11:55:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 886203 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="GsbQFQ+p"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4026Wf04d0z9sVh for ; Thu, 15 Mar 2018 22:56:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751832AbeCOL4B (ORCPT ); Thu, 15 Mar 2018 07:56:01 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:34034 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751302AbeCOLzv (ORCPT ); Thu, 15 Mar 2018 07:55:51 -0400 Received: by mail-wr0-f193.google.com with SMTP id o8so8035942wra.1 for ; Thu, 15 Mar 2018 04:55:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q3q9PRMA5EPH9HvpB896Y2fd/Dwgod9dm0kyC99EDb4=; b=GsbQFQ+pDYTPkRR922Q4QygK0tlcZJr19j2E9Uo9dHlBg3Strx7I8qipNm43u+Re6o 7HMeyYv3tvSLGAI5FcL6PCVCjC/2/IsVfMmXmwZITSEE8IxqCCTFbeqzrVm1Svm1pR79 AO04X3EVm3Ktjt3vrU8SGAcNepfIlizKfOsV3I7mSegctBKbm+qdZXQDVFmW2UBPw+yA gNbh7D6osjlYHveURvkafk4T8btLvWP/SsI/cMqEVQxaVBFnEmNHdD9EqGFWgfst18m3 LYhgX1ZG4LnYXwaXLOK5CUwhO38itHKnIJszdYrOfaEO8DDEQeELh6bsfgqlyilMEfIt chtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q3q9PRMA5EPH9HvpB896Y2fd/Dwgod9dm0kyC99EDb4=; b=V9ni8TM9TpAlY1H8TBHoBB/C/+FSwP3MrCdKvs447UZiMd6iVAxL6XJm5nUMQwGKHF lXFoRcDXNiddVoxBTBpIrEvV4+kDaTf6tTHBefKnZGPkHdNEFtkot+Ape+jADo4rWRep j9kxo6Tukb0GswIo5QQC2DEJ64LppSQCekaIVynn04D+CIaVifyniMXXv7RnBX6hunq0 wsZxoh2pGpkrjmb3oHMYN4rCUKHaC33y8vrg0fOtnB+dKskp+NLMOOBH+JfofduMjNo9 M/B1K2Ai+pdMi5xWZbb/ZNsmbAyY6t4tTBzz3NbqkHKvEgVvBwug3gtB6SRiCmJTuakF x74g== X-Gm-Message-State: AElRT7GeH7I54Gvn6nvz/fFNT/yrA0JS2NMHPXksyOleLbionNKebPWW mtExkD68y8pO2A25ATnmQgMtRQ== X-Google-Smtp-Source: AG47ELuOMXVZCUzeZyCwiAXOwWOn4lpgV5Z9ESsc0pOWcV+zGU5k82W2oPtDHyNp5oro8jQtgh9Pvg== X-Received: by 10.223.146.133 with SMTP id 5mr7155821wrn.109.1521114950214; Thu, 15 Mar 2018 04:55:50 -0700 (PDT) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id e18sm4483318wmc.21.2018.03.15.04.55.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 15 Mar 2018 04:55:49 -0700 (PDT) From: Jerome Brunet To: Kevin Hilman , Carlo Caione , Neil Armstrong Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/4] dt-bindings: clock: meson: update documentation with hhi syscon Date: Thu, 15 Mar 2018 12:55:42 +0100 Message-Id: <20180315115545.1884-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180315115545.1884-1-jbrunet@baylibre.com> References: <20180315115545.1884-1-jbrunet@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The HHI register region hosts more than just clocks and needs to accessed drivers other than the clock controller, such as the display driver. This register region should be managed by syscon. It is already the case on gxbb/gxl and it soon will be on axg. The clock controllers must use this system controller instead of directly mapping the registers. This changes the bindings of gxbb and axg's clock controllers. This is due to an initial 'incomplete' knowledge of these SoCs, which is why the meson bindings are unstable ATM. Signed-off-by: Jerome Brunet --- .../devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e2b377ed6f91..e950599566a9 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -10,9 +10,6 @@ Required Properties: "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. -- reg: physical base address of the clock controller and length of memory - mapped region. - - #clock-cells: should be 1. Each clock is assigned an identifier and client nodes can use this identifier @@ -20,13 +17,22 @@ to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be used in device tree sources. +Parent node should have the following properties : +- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or + "amlogic,meson-axg-hhi-sysctrl" +- reg: base address and size of the HHI system control register space. + Example: Clock controller node: - clkc: clock-controller@c883c000 { +sysctrl: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { #clock-cells = <1>; compatible = "amlogic,gxbb-clkc"; - reg = <0x0 0xc883c000 0x0 0x3db>; }; +}; Example: UART controller node that consumes the clock generated by the clock controller: