From patchwork Mon Nov 20 19:50:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 839739 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ygfTf71fdz9s7v for ; Tue, 21 Nov 2017 06:50:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752733AbdKTTuj (ORCPT ); Mon, 20 Nov 2017 14:50:39 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:35281 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752694AbdKTTui (ORCPT ); Mon, 20 Nov 2017 14:50:38 -0500 Received: by mail-pg0-f68.google.com with SMTP id l19so8209965pgo.2 for ; Mon, 20 Nov 2017 11:50:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:cc:from:to; bh=OO8VkgPidcOx6hWj5mBCAztx5IKTWw6gtS1c752diBQ=; b=UHg0UrIGuEcF1nYRu7ZQ7PKlC3eD4BBNVJuNHGZy8cTUmVA9DDpHbTqrCmKlz43n62 2yOPQeiwRwGUkAABmXqSYYQyDD+ttoyeEpjIid7A9GaNBQ83YpubHGijLyHXF+uX4ZfI zhN5wskv8aiRQwzYWDeP3O8z8iAms4wzUFzS6d/aEzrQg4uocxsiuW8T/kmN8m7bc4dU twFHYJZl4uCzs2VgomdydXdevEqm373RhS1goJZL2FUl1u1EhD6Kh48mIU7vNwXm0oGH /0KLCg2CSCjGlLOkqyVNM9wr6HmpgQPTesX0AnUU7yBUZYC4khMJrqRi9m8URdErP1Yn 1hlA== X-Gm-Message-State: AJaThX7ubr2imWPXkzEl5z+6pbRwt/uWcYVNjw341T7uRg6WlXtbVK+7 zZE9DgAyX74QwUyzV+1PX8fO+A== X-Google-Smtp-Source: AGs4zMbBqZx/wFmwi4L0/2M2+dKxlQlZkM/BusQP5tYHFKcHOA61vdgZgLoFrgWfLFhUXCOjgtVmaQ== X-Received: by 10.84.234.198 with SMTP id i6mr15127170plt.260.1511207437572; Mon, 20 Nov 2017 11:50:37 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id d28sm21704790pfb.105.2017.11.20.11.50.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Nov 2017 11:50:36 -0800 (PST) Subject: [PATCH] dt-bindings: Add an enable method to RISC-V Date: Mon, 20 Nov 2017 11:50:22 -0800 Message-Id: <20171120195022.2307-1-palmer@sifive.com> X-Mailer: git-send-email 2.13.6 Cc: patches@groups.riscv.org, linux-kernel@vger.kernel.org, Palmer Dabbelt From: Palmer Dabbelt To: mark.rutland@arm.com, robh+dt@kernel.org, devicetree@vger.kernel.org Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org RISC-V doesn't currently specify a mechanism for enabling or disabling CPUs. Instead, we assume that all CPUs are enabled on boot, and if someone wants to save power we instead put a CPU to sleep via a WFI loop. This patch adds "enable-method" to the RISC-V CPU binding, which currently only has the value "none". This allows us to change the enable method in the future. CC: Mark Rutland Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/cpus.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af5dc3..dd9e1ae197e2 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -82,6 +82,11 @@ described below. Value type: Definition: Contains the RISC-V ISA string of this hart. These ISA strings are defined by the RISC-V ISA manual. + - cpu-enable-method: + Usage: required + Value type: + Definition: Must be one of + "none": This CPU's state cannot be changed. Example: SiFive Freedom U540G Development Kit --------------------------------------------- @@ -105,6 +110,7 @@ Linux is allowed to run on. reg = <0>; riscv,isa = "rv64imac"; status = "disabled"; + enable-method = "none"; L10: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -130,6 +136,7 @@ Linux is allowed to run on. reg = <1>; riscv,isa = "rv64imafdc"; status = "okay"; + enable-method = "none"; tlb-split; L13: interrupt-controller { #interrupt-cells = <1>;