From patchwork Wed Aug 30 15:19:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 807681 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xj8ML6D5Fz9sN7 for ; Thu, 31 Aug 2017 01:20:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751650AbdH3PUK (ORCPT ); Wed, 30 Aug 2017 11:20:10 -0400 Received: from muru.com ([72.249.23.125]:38844 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751625AbdH3PUJ (ORCPT ); Wed, 30 Aug 2017 11:20:09 -0400 Received: from sampyla.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 278DF82B9; Wed, 30 Aug 2017 15:20:31 +0000 (UTC) From: Tony Lindgren To: linux-omap@vger.kernel.org Cc: =?utf-8?q?Beno=C3=AEt_Cousson?= , devicetree@vger.kernel.org, Liam Girdwood , Mark Brown , Mark Rutland , Peter Ujfalusi , Rob Herring Subject: [PATCH 12/17] ARM: dts: Add missing aess node and binding for omap4 Date: Wed, 30 Aug 2017 08:19:48 -0700 Message-Id: <20170830151953.30856-13-tony@atomide.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170830151953.30856-1-tony@atomide.com> References: <20170830151953.30856-1-tony@atomide.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On omap4 we're missing the aess node with it's related "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Liam Girdwood Cc: Mark Brown Cc: Mark Rutland Cc: Peter Ujfalusi Cc: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/sound/ti-aess.txt | 33 ++++++++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 8 ++++++ 2 files changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/ti-aess.txt diff --git a/Documentation/devicetree/bindings/sound/ti-aess.txt b/Documentation/devicetree/bindings/sound/ti-aess.txt new file mode 100644 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti-aess.txt @@ -0,0 +1,33 @@ +Texas Instruments Audio Engine Subsystem (AESS) binding + +AESS performs real-time signal processing on TI SoCs. + + +Required properties: + +compatible: Shall be one of the following: + "ti,omap4-aess" + +reg: Shall contain the device instance IO range + +interrupts: Shall contain the device instance interrupt + + +Optional properties: + +reg-names: Shall contain the IO range names if multiple IO + ranges are used by the SoC + +ti,hwmods: Shall contain the TI interconnect module name if needed + by the SoC + + +Example: + + aess: aess@401f1000 { + compatible = "ti,omap4-aess"; + reg = <0x401f1000 0x400>, /* MPU private access */ + <0x490f1000 0x400>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + ti,hwmods = "aess"; + }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -793,6 +793,14 @@ ti,hwmods = "slimbus1"; }; + aess: aess@401f1000 { + compatible = "ti,omap4-aess"; + reg = <0x401f1000 0x400>, /* MPU private access */ + <0x490f1000 0x400>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + ti,hwmods = "aess"; + }; + mcbsp4: mcbsp@48096000 { compatible = "ti,omap4-mcbsp"; reg = <0x48096000 0xff>; /* L4 Interconnect */