diff mbox series

[12/17] ARM: dts: Add missing aess node and binding for omap4

Message ID 20170830151953.30856-13-tony@atomide.com
State Changes Requested, archived
Headers show
Series Fix missing device tree hwmods and IO ranges omap variants | expand

Commit Message

Tony Lindgren Aug. 30, 2017, 3:19 p.m. UTC
On omap4 we're missing the aess node with it's related "ti,hwmods"
property that the SoC interconnect code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 .../devicetree/bindings/sound/ti-aess.txt          | 33 ++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       |  8 ++++++
 2 files changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/ti-aess.txt

Comments

Peter Ujfalusi Aug. 31, 2017, 5:54 a.m. UTC | #1



Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

On 2017-08-30 18:19, Tony Lindgren wrote:
> On omap4 we're missing the aess node with it's related "ti,hwmods"
> property that the SoC interconnect code needs.
> 
> Note that this will only show up as a bug with "doesn't have
> mpu register target base" boot errors when the legacy platform
> data is removed.
> 
> Cc: Liam Girdwood <lgirdwood@gmail.com>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  .../devicetree/bindings/sound/ti-aess.txt          | 33 ++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       |  8 ++++++
>  2 files changed, 41 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/sound/ti-aess.txt
> 
> diff --git a/Documentation/devicetree/bindings/sound/ti-aess.txt b/Documentation/devicetree/bindings/sound/ti-aess.txt
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/ti-aess.txt
> @@ -0,0 +1,33 @@
> +Texas Instruments Audio Engine Subsystem (AESS) binding
> +
> +AESS performs real-time signal processing on TI SoCs.
> +
> +
> +Required properties:
> +
> +compatible: Shall be one of the following:
> +	    "ti,omap4-aess"
> +
> +reg: Shall contain the device instance IO range
> +
> +interrupts: Shall contain the device instance interrupt
> +
> +
> +Optional properties:
> +
> +reg-names: Shall contain the IO range names if multiple IO
> +	   ranges are used by the SoC
> +
> +ti,hwmods: Shall contain the TI interconnect module name if needed
> +	   by the SoC
> +
> +
> +Example:
> +
> +	aess: aess@401f1000 {
> +		compatible = "ti,omap4-aess";
> +		reg = <0x401f1000 0x400>, /* MPU private access */
> +		      <0x490f1000 0x400>; /* L3 Interconnect */
> +		reg-names = "mpu", "dma";
> +		ti,hwmods = "aess";
> +	};
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -793,6 +793,14 @@
>  			ti,hwmods = "slimbus1";
>  		};
>  
> +		aess: aess@401f1000 {
> +			compatible = "ti,omap4-aess";
> +			reg = <0x401f1000 0x400>, /* MPU private access */
> +			      <0x490f1000 0x400>; /* L3 Interconnect */
> +			reg-names = "mpu", "dma";
> +			ti,hwmods = "aess";

status = "disabled"

> +		};

Similar comment applies to AESS as to the McASP. We don't have driver
for it and we most likely not going to have.
But the binding is not correct in any case. The latest official Android
kernel is 3.4(ish) to support AESS/ABE. I have rewritten the whole thing
as an effort to upstream it and maintained the code up to 3.15. There
the DT node looks like this:

aess: aess@0x401f1000 {
	compatible = "ti,omap4-aess";
	reg = <0x401f1000 0x3ff>, /* MPU private access */
		<0x40180000 0xffff>, /* DMEM - MPU */
		<0x401a0000 0x1fff>, /* CMEM - MPU */
		<0x401c0000 0x5fff>, /* SMEM - MPU */
		<0x401e0000 0x1fff>, /* PMEM - MPU */
		<0x490f1000 0x3ff>, /* L3 Interconnect */
		<0x49080000 0xffff>, /* DMEM - MPU */
		<0x490a0000 0x1fff>, /* CMEM - MPU */
		<0x490ce000 0x5fff>, /* SMEM - MPU */
		<0x490e0000 0x1fff>; /* PMEM - MPU */
	reg-names = "mpu", "dmem", "cmem", "smem", "pmem",
			"dma","dmem_dma", "cmem_dma", "smem_dma",
			"pmem_dma";
	interrupts = <0 99 0x4>;
	ti,hwmods = "aess";
	dmas = <&sdma 101>,
		<&sdma 102>,
		<&sdma 103>,
		<&sdma 104>,
		<&sdma 105>,
		<&sdma 106>,
		<&sdma 107>,
		<&sdma 108>;
	dma-names = "fifo0", "fifo1", "fifo2", "fifo3", "fifo4",
			"fifo5", "fifo6", "fifo7";
};

This is more closer to what we might need to describe AESS, but it might
be not correct if I ever have the time to forward port and convert it to
current upstream framework (DPCM, graph, whatever)

> +
>  		mcbsp4: mcbsp@48096000 {
>  			compatible = "ti,omap4-mcbsp";
>  			reg = <0x48096000 0xff>; /* L4 Interconnect */
> 

- Péter

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Tony Lindgren Aug. 31, 2017, 2:51 p.m. UTC | #2
* Peter Ujfalusi <peter.ujfalusi@ti.com> [170830 22:54]:
> On 2017-08-30 18:19, Tony Lindgren wrote:
> > +		aess: aess@401f1000 {
> > +			compatible = "ti,omap4-aess";
> > +			reg = <0x401f1000 0x400>, /* MPU private access */
> > +			      <0x490f1000 0x400>; /* L3 Interconnect */
> > +			reg-names = "mpu", "dma";
> > +			ti,hwmods = "aess";
> 
> status = "disabled"

That could be done for it's children if needed like I replied in
the McASP patch as this is for the interconnect target module.
And this will need to just use the "ti,sysc-type2" compatible.

> Similar comment applies to AESS as to the McASP. We don't have driver
> for it and we most likely not going to have.

OK

> But the binding is not correct in any case. The latest official Android
> kernel is 3.4(ish) to support AESS/ABE. I have rewritten the whole thing
> as an effort to upstream it and maintained the code up to 3.15. There
> the DT node looks like this:
> 
> aess: aess@0x401f1000 {
> 	compatible = "ti,omap4-aess";
> 	reg = <0x401f1000 0x3ff>, /* MPU private access */
> 		<0x40180000 0xffff>, /* DMEM - MPU */
> 		<0x401a0000 0x1fff>, /* CMEM - MPU */
> 		<0x401c0000 0x5fff>, /* SMEM - MPU */
> 		<0x401e0000 0x1fff>, /* PMEM - MPU */
> 		<0x490f1000 0x3ff>, /* L3 Interconnect */
> 		<0x49080000 0xffff>, /* DMEM - MPU */
> 		<0x490a0000 0x1fff>, /* CMEM - MPU */
> 		<0x490ce000 0x5fff>, /* SMEM - MPU */
> 		<0x490e0000 0x1fff>; /* PMEM - MPU */
> 	reg-names = "mpu", "dmem", "cmem", "smem", "pmem",
> 			"dma","dmem_dma", "cmem_dma", "smem_dma",
> 			"pmem_dma";
> 	interrupts = <0 99 0x4>;
> 	ti,hwmods = "aess";
> 	dmas = <&sdma 101>,
> 		<&sdma 102>,
> 		<&sdma 103>,
> 		<&sdma 104>,
> 		<&sdma 105>,
> 		<&sdma 106>,
> 		<&sdma 107>,
> 		<&sdma 108>;
> 	dma-names = "fifo0", "fifo1", "fifo2", "fifo3", "fifo4",
> 			"fifo5", "fifo6", "fifo7";
> };
> 
> This is more closer to what we might need to describe AESS, but it might
> be not correct if I ever have the time to forward port and convert it to
> current upstream framework (DPCM, graph, whatever)

Yeah OK thanks. If there ever is a driver for it, those can then
be added as child nodes of the "ti,sysc-type2" interconnect target
node.

Regards,

Tony
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diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/sound/ti-aess.txt b/Documentation/devicetree/bindings/sound/ti-aess.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ti-aess.txt
@@ -0,0 +1,33 @@ 
+Texas Instruments Audio Engine Subsystem (AESS) binding
+
+AESS performs real-time signal processing on TI SoCs.
+
+
+Required properties:
+
+compatible: Shall be one of the following:
+	    "ti,omap4-aess"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+reg-names: Shall contain the IO range names if multiple IO
+	   ranges are used by the SoC
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+	   by the SoC
+
+
+Example:
+
+	aess: aess@401f1000 {
+		compatible = "ti,omap4-aess";
+		reg = <0x401f1000 0x400>, /* MPU private access */
+		      <0x490f1000 0x400>; /* L3 Interconnect */
+		reg-names = "mpu", "dma";
+		ti,hwmods = "aess";
+	};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -793,6 +793,14 @@ 
 			ti,hwmods = "slimbus1";
 		};
 
+		aess: aess@401f1000 {
+			compatible = "ti,omap4-aess";
+			reg = <0x401f1000 0x400>, /* MPU private access */
+			      <0x490f1000 0x400>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			ti,hwmods = "aess";
+		};
+
 		mcbsp4: mcbsp@48096000 {
 			compatible = "ti,omap4-mcbsp";
 			reg = <0x48096000 0xff>; /* L4 Interconnect */