From patchwork Mon Jun 5 17:31:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 771369 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3whMNR1P5Wz9s0m for ; Tue, 6 Jun 2017 03:33:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751825AbdFERdI (ORCPT ); Mon, 5 Jun 2017 13:33:08 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:57532 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751686AbdFERdH (ORCPT ); Mon, 5 Jun 2017 13:33:07 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 148C6CA4BB17E; Mon, 5 Jun 2017 18:32:56 +0100 (IST) Received: from localhost (10.20.1.33) by hhmail02.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 5 Jun 2017 18:32:59 +0100 From: Paul Burton To: CC: "David S . Miller" , , Eric Dumazet , Jarod Wilson , Tobias Klauser , Paul Burton , Mark Rutland , Rob Herring , Subject: [PATCH v4 3/7] dt-bindings: net: Document Intel pch_gbe binding Date: Mon, 5 Jun 2017 10:31:32 -0700 Message-ID: <20170605173136.10795-4-paul.burton@imgtec.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170605173136.10795-1-paul.burton@imgtec.com> References: <20170602234042.22782-1-paul.burton@imgtec.com> <20170605173136.10795-1-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.20.1.33] Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce documentation for a device tree binding for the Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) device. Although this is a PCIe device & thus largely auto-detectable, this binding will be used to provide the driver with the PHY reset GPIO. Signed-off-by: Paul Burton Cc: David S. Miller Cc: Eric Dumazet Cc: Jarod Wilson Cc: Mark Rutland Cc: Rob Herring Cc: Tobias Klauser Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org --- Changes in v4: None Changes in v3: - New patch. Changes in v2: None Documentation/devicetree/bindings/net/pch_gbe.txt | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt diff --git a/Documentation/devicetree/bindings/net/pch_gbe.txt b/Documentation/devicetree/bindings/net/pch_gbe.txt new file mode 100644 index 000000000000..5de479c26b04 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pch_gbe.txt @@ -0,0 +1,25 @@ +Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) + +Required properties: +- compatible: Should be the PCI vendor & device ID, eg. "pci8086,8802". +- reg: Should be a PCI device number as specified by the PCI bus + binding to IEEE Std 1275-1994. +- phy-reset-gpios: Should be a GPIO list containing a single GPIO that + resets the attached PHY when active. + +Example: + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 + GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + };