From patchwork Fri Nov 25 13:01:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 699225 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tQGSr5CsHz9s9c for ; Sat, 26 Nov 2016 00:02:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.b="fToaZJIR"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754331AbcKYNCb (ORCPT ); Fri, 25 Nov 2016 08:02:31 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:36213 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753335AbcKYNC1 (ORCPT ); Fri, 25 Nov 2016 08:02:27 -0500 Received: by mail-wm0-f66.google.com with SMTP id m203so7712246wma.3; Fri, 25 Nov 2016 05:02:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fU8RHfUaLfHwrszcxBtiD4Wy6Aw9W4oCMpCHPmf/oaU=; b=fToaZJIRGi/xu4U5n5mC1YdoCZGmOf1kS464+9lPOKhMpse7qWAl2vkt5E25VlzwYv lzl9roYKmxkgzdb7pS1iYxx4VcYXb6gXkpWbswtuWL7V6OVds8h5ce3r38u3EuGgw7zH JxULmofHtQthaDFl45yuf0FcJX9tDWc83PpS6mYP/dvvwCaw7atMQB8E/j2WvwmUpo5L oKsQIHkpmexFTCSGs3ZrnmnrFy/WpeWFYc9S0Rs230BK58u14+Q0JNvdkPowMjvPvuUi uffGLSUKzaF9zjmi2Fc5fCUSlBnfvG/oZcWrFdVTDhv4UZ+Pg2feQXuUCVtfM0kDm8nM d9tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fU8RHfUaLfHwrszcxBtiD4Wy6Aw9W4oCMpCHPmf/oaU=; b=NrPYzapEwIASoXi750MYXGfPKCuqRbp3Jglur1WKrHhdt74oJ8xBvQoaq8loaje8ti iKtKqv0+Cq8BcjHzHZ4TmvACoGtUPEbBKW5vTH57ooOkDkAw0sNmv1N+P5e9TEF9FPFY BQpXGC4p8RCE7VwwAt86txxhixj5gpibGvXbKEtBHPtBC6HymY2PeaFMFS50rPmTvBIN l+lGj7CmsE2Lwg/6kwDPOexooAesBw3x7y/RJTwfKzyYBuKE10+PYbuZf4JTx3c0WAoA DmCBD+z1/ceHJQTtoNDs7I6jt7bfz+RS7bMjMsJsqLgEQVE67EMkF/YZkIGpPrTvv9WP OKUA== X-Gm-Message-State: AKaTC00LOeq94LXk6JvECZfWKbP+HRmaZ7RZAWtVDYBE9RO1iIo5TpdhFXzZgsZF/ZImtg== X-Received: by 10.28.74.25 with SMTP id x25mr7836960wma.74.1480078945647; Fri, 25 Nov 2016 05:02:25 -0800 (PST) Received: from blackbox.darklights.net ([2003:dc:d3d3:9204:9426:48db:352f:a6de]) by smtp.googlemail.com with ESMTPSA id ua15sm46937433wjb.1.2016.11.25.05.02.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Nov 2016 05:02:24 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, davem@davemloft.net, khilman@baylibre.com, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, alexandre.torgue@st.com, peppe.cavallaro@st.com, will.deacon@arm.com, catalin.marinas@arm.com, carlo@caione.org, f.fainelli@gmail.com, Martin Blumenstingl Subject: [PATCH v2 1/7] net: dt-bindings: add RGMII TX delay configuration to meson8b-dwmac Date: Fri, 25 Nov 2016 14:01:50 +0100 Message-Id: <20161125130156.17879-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161125130156.17879-1-martin.blumenstingl@googlemail.com> References: <20161124143417.10178-1-martin.blumenstingl@googlemail.com> <20161125130156.17879-1-martin.blumenstingl@googlemail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This allows configuring the RGMII TX clock delay. The RGMII clock is generated by underlying hardware of the the Meson 8b / GXBB DWMAC glue. The configuration depends on the actual hardware (no delay may be needed due to the design of the actual circuit, the PHY might add this delay, etc.). Signed-off-by: Martin Blumenstingl --- Documentation/devicetree/bindings/net/meson-dwmac.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt index 89e62dd..f8bc540 100644 --- a/Documentation/devicetree/bindings/net/meson-dwmac.txt +++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt @@ -25,6 +25,20 @@ Required properties on Meson8b and newer: - "clkin0" - first parent clock of the internal mux - "clkin1" - second parent clock of the internal mux +Optional properties on Meson8b and newer: +- amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided + by this driver) in nanoseconds. Allowed values + are: 0ns, 2ns, 4ns, 6ns. + This must be configured when the phy-mode is + "rgmii" (typically a value of 2ns is used in + this case). + When phy-mode is set to "rgmii-id" or + "rgmii-txid" the TX clock delay is already + provided by the PHY. In that case this + property should be set to 0ns (which disables + the TX clock delay in the MAC to prevent the + clock from going off because both PHY and MAC + are adding a delay). Example for Meson6: