From patchwork Thu Sep 17 06:32:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 518728 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 9446D1401DA for ; Thu, 17 Sep 2015 16:32:53 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=JTj8eKY4; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753310AbbIQGcx (ORCPT ); Thu, 17 Sep 2015 02:32:53 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:34585 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753356AbbIQGcw (ORCPT ); Thu, 17 Sep 2015 02:32:52 -0400 Received: by padhy16 with SMTP id hy16so11604869pad.1; Wed, 16 Sep 2015 23:32:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=bgW3lLtkX0Dko20StHzuGlFSQ8snzUAu9Z/CkEDBuZk=; b=JTj8eKY4I9/RIte44EpCTtp5eO6zunIm/CPi9PniBeowAm7vA6VWPafcgIURp3OkdR rnSwoPK9xs9dxnYY32yQDlAxIxNluyYDIwVk4B37EtV8s/BqP31nvvDWvvMAMvf6OnJu rLS9cRraPJKlyvFx2Z9WrK75fDfAoe3wjzBhOx9fbJT5+aifirbeDQndTlEywl3cXtcU Gr4UIugNMlzCEv9nNpuTgig4Qms44zVAsSxpkhaeC81aPyQf7/q7BKeMdpRDJ48SVy7O ekCi/DQYKJHKgDDGa4k1UcnZqQ4n+TN4RjBLIf2coKi63CTWCifMeET/R4R0qNLFTJST 0j0g== X-Received: by 10.66.236.74 with SMTP id us10mr69669673pac.64.1442471571852; Wed, 16 Sep 2015 23:32:51 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by smtp.gmail.com with ESMTPSA id j16sm1673261pbq.23.2015.09.16.23.32.48 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Sep 2015 23:32:50 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, keita.kobayashi.ym@renesas.com, horms@verge.net.au, geert@linux-m68k.org, laurent.pinchart@ideasonboard.com, Magnus Damm Date: Thu, 17 Sep 2015 15:32:50 +0900 Message-Id: <20150917063250.26016.99820.sendpatchset@little-apple> In-Reply-To: <20150917063240.26016.93772.sendpatchset@little-apple> References: <20150917063240.26016.93772.sendpatchset@little-apple> Subject: [PATCH v3 01/09] devicetree: bindings: Renesas APMU and SMP Enable method Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Magnus Damm Add DT binding documentation for the APMU hardware and add "renesas,apmu" to the list of enable methods for the ARM cpus. Signed-off-by: Magnus Damm --- Changes since V2: - s/Until/Unit/g - thanks Geert! Changes since V1: - None Documentation/devicetree/bindings/arm/cpus.txt | 1 Documentation/devicetree/bindings/power/renesas,apmu.txt | 31 ++++++++++++++ 2 files changed, 32 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/Documentation/devicetree/bindings/arm/cpus.txt +++ work/Documentation/devicetree/bindings/arm/cpus.txt 2015-09-16 20:32:46.710513000 +0900 @@ -198,6 +198,7 @@ nodes to be present and contain the prop "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "renesas,apmu" "rockchip,rk3066-smp" "ste,dbx500-smp" --- /dev/null +++ work/Documentation/devicetree/bindings/power/renesas,apmu.txt 2015-09-16 20:42:09.000513000 +0900 @@ -0,0 +1,31 @@ +DT bindings for the Renesas Advanced Power Management Unit + +Renesas R-Car line of SoCs utilize one or more APMU hardware units +for CPU core power domain control including SMP boot and CPU Hotplug. + +Required properties: + +- compatible: Should be "renesas,apmu-", "renesas,apmu" as fallback. + Examples with soctypes are: + - "renesas,apmu-r8a7790" (R-Car H2) + - "renesas,apmu-r8a7791" (R-Car M2-W) + - "renesas,apmu-r8a7792" (R-Car V2H) + - "renesas,apmu-r8a7793" (R-Car M2-N) + - "renesas,apmu-r8a7794" (R-Car E2) + +- reg: Base address and length of the I/O registers used by the APMU. + +- cpus: This node contains a list of CPU cores, which should match the order + of CPU cores used by the WUPCR and PSTR reigsters in the Advanced Power + Management Unit section of the device's datasheet. + + +Example: + +This shows the r8a7791 APMU that can control CPU0 and CPU1. + + apmu@e6152000 { + compatible = "renesas,apmu-r8a7791", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + };