From patchwork Tue Apr 28 14:17:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Fuzzey X-Patchwork-Id: 465565 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 18A901400B7 for ; Wed, 29 Apr 2015 00:17:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965729AbbD1ORl (ORCPT ); Tue, 28 Apr 2015 10:17:41 -0400 Received: from ip83.parkeon.com ([213.152.31.83]:58493 "EHLO mta2.parkeon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965663AbbD1ORk (ORCPT ); Tue, 28 Apr 2015 10:17:40 -0400 Received: from time001.besancon.parkeon.com ([10.32.16.23] helo=mail.besancon.parkeon.com) by mta2.parkeon.com with esmtp (Exim 4.82) (envelope-from ) id 1Yn6KO-0004Vb-6x; Tue, 28 Apr 2015 16:17:36 +0200 Received: from [10.32.51.184] (port=54648 helo=[127.0.0.1]) by mail.besancon.parkeon.com with esmtp (Exim 4.71) (envelope-from ) id 1Yn6KQ-0007e4-Fm; Tue, 28 Apr 2015 16:17:38 +0200 Subject: [PATCH 1/2] Regulator: mc34708: Add DT binding documentation To: Mark Brown , Liam Girdwood , Rob Herring From: Martin Fuzzey Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Date: Tue, 28 Apr 2015 16:17:38 +0200 Message-ID: <20150428141738.16243.18377.stgit@localhost> In-Reply-To: <20150428141736.16243.57292.stgit@localhost> References: <20150428141736.16243.57292.stgit@localhost> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Spam-Report: Spam detection software, running on the system "srv025-bes.parkeon.com", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Signed-off-by: Martin Fuzzey --- .../bindings/regulator/mc34708-regulator.txt | 198 ++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/mc34708-regulator.txt [...] Content analysis details: (-2.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 URIBL_BLOCKED ADMINISTRATOR NOTICE: The query to URIBL was blocked. See http://wiki.apache.org/spamassassin/DnsBlocklists#dnsbl-block for more information. [URIs: parkeon.com] -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP -1.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain X-Spam-Score: -2.0 (--) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Martin Fuzzey --- .../bindings/regulator/mc34708-regulator.txt | 198 ++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/mc34708-regulator.txt -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/regulator/mc34708-regulator.txt b/Documentation/devicetree/bindings/regulator/mc34708-regulator.txt new file mode 100644 index 0000000..35efae0 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mc34708-regulator.txt @@ -0,0 +1,198 @@ +Regulators included in the Freescale MC34708 PMIC + +Required properties: +- compatible: "fsl,mc34708" +- reg: I2C slave address + + +Regulators subnode: +------------------- +This node contains children following the standard regulator binding format +described in Documentation/devicetree/bindings/regulator/regulator.txt + +The allowed node names are: + Switchers: + sw1, sw2, sw3, sw4a, sw4b, sw5, swbst + LDOs: + vpll, vrefddr, vusb, vusb2, vdac, vgen1, vgen2 + +The mode values are: + Switchers: + 1 : Pulse Frequency Modulation (PFM) [for low loads] + 2 : Auto + 3 : Pulse Width Modulation (PWM) [for high loads] + LDOs: + 1 : Low power + 2 : Normal + +Optional properties: +The input supply of regulators are the optional properties on the +regulator node. + +- vinsw1-supply : phandle to input supply for sw1 regulator +- vinsw2-supply : phandle to input supply for sw2 regulator +- vinsw3-supply : phandle to input supply for sw3 regulator +- vinsw4a-supply : phandle to input supply for sw4a regulator +- vinsw4b-supply : phandle to input supply for sw4b regulator +- vinsw5-supply : phandle to input supply for sw5 regulator +- vinswbst-supply : phandle to input supply for swbst regulator +- vinrefddr-supply : phandle to input supply for vrefddr regulator (/2) + + +Example: +&i2c3 { + pmic: mc34708@08 { + compatible = "fsl,mc34708"; + reg = <0x08>; + regulators { +#define PMIC_REGMODE_SW_PFM 1 +#define PMIC_REGMODE_SW_AUTO 2 +#define PMIC_REGMODE_SW_PWM 3 +#define PMIC_REGMODE_LDO_LP 1 +#define PMIC_REGMODE_LDO_NORMAL 2 + + vinrefddr-supply = <&pmic_sw4a_reg>; + pmic_sw1_reg: sw1 { + /* CPU Core */ + regulator-name = "SW1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1437500>; + regulator-boot-on; + regulator-always-on; + regulator-initial-mode = ; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + regulator-mode = ; + }; + }; + + pmic_sw2_reg: sw2 { + /* SOC Periperals */ + regulator-name = "SW2"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1437500>; + regulator-boot-on; + regulator-always-on; + regulator-initial-mode = ; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + regulator-mode = ; + }; + }; + + pmic_sw3_reg: sw3 { + regulator-name = "SW3"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1425000>; + }; + + pmic_sw4a_reg: sw4a { + /* DDR Ram */ + regulator-name = "SW4A"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-initial-mode = ; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + pmic_sw5_reg: sw5 { + /* 1v8 power */ + regulator-name = "SW5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + regulator-initial-mode = ; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + pmic_swbst_reg: swbst { + regulator-name = "SWBST"; + regulator-boot-on; + regulator-always-on; + regulator-initial-mode = ; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pmic_vpll_reg: vpll { + regulator-name = "VPLL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + pmic_vrefddr_reg: vrefddr { + regulator-name = "VREFDDR"; + regulator-boot-on; + regulator-always-on; + }; + + pmic_vusb_reg: vusb { + regulator-name = "VUSB"; + regulator-boot-on; + regulator-always-on; + }; + + pmic_vusb2_reg: vusb2 { + regulator-name = "VUSB2"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pmic_vdac_reg: vdac { + regulator-name = "VDAC"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + regulator-initial-mode = ; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + + pmic_vgen1_reg: vgen1 { + regulator-name = "VGEN1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pmic_vgen2_reg: vgen2 { + regulator-name = "VGEN2"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-initial-mode = ; + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = ; + }; + }; + }; + }; +};