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[06/24] Documentation: DT bindings: add more chip compatible strings for Tegra APB_MISC

Message ID 20150128234937.20644.82091.stgit@dusk.lan
State Needs Review / ACK, archived
Headers show


Context Check Description
robh/checkpatch warning total: 1 errors, 0 warnings, 0 lines checked
robh/patch-applied success

Commit Message

Paul Walmsley Jan. 28, 2015, 11:49 p.m. UTC
Add compatible strings for the APB_MISC IP blocks present on several Tegra
chips.  The primary objective here is to avoid checkpatch warnings,


Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: devicetree@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
 .../bindings/misc/nvidia,tegra20-apbmisc.txt       |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

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diff mbox


diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
index b97b8bef1fe5..2723f3e4e52d 100644
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
@@ -3,9 +3,10 @@  NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
 Required properties:
 - compatible : should be:
-       "nvidia,tegra30-apbmisc"
-       "nvidia,tegra114-apbmisc"
-       "nvidia,tegra124-apbmisc"
+       "nvidia,tegra30-apbmisc" (not yet matched in the driver)
+       "nvidia,tegra114-apbmisc" (not yet matched in the driver)
+       "nvidia,tegra124-apbmisc" (not yet matched in the driver)
+       "nvidia,tegra132-apbmisc" (not yet matched in the driver)
 - reg: Should contain 2 entries: the first entry gives the physical address
        and length of the registers which contain revision and debug features.
        The second entry gives the physical address and length of the