From patchwork Fri Jul 30 09:34:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 1511564 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=cj7sLJt9; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Gbj0V2rb0z9sXM for ; Fri, 30 Jul 2021 19:34:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238208AbhG3Jef (ORCPT ); Fri, 30 Jul 2021 05:34:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:51888 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238356AbhG3Jec (ORCPT ); Fri, 30 Jul 2021 05:34:32 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D74B061019; Fri, 30 Jul 2021 09:34:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627637667; bh=AyZq286GxOzlTPT6NwaDtxxaeeo+pRSi6ddl1AxdRy4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cj7sLJt9ZYR4ZSGjKUviFXa1tBXGUFeNKogl5uby272IwYnNM7joGPvCPA3/hBjnB RAtrkN2nwigreOu6vhnjK6eximxGUGECRjRBeQ9zoKbeEt2H4j8MFSKwBa7Xv+eg8Q Sce5iB19zLdBOv7slmotk7Ky3ddLJLnwBLMfugv//saK3XdJp0HF1w/Sl3DVzqiS3L V2eSmAV4o4298JSDdyFctl6aylq9t3FrEAyrRSCiI0RLBsHgBuoWdscLfx1e35yqKq 3e1z/GHUEf75Y7T0LZBLGC0Iuj00HyvDIrKt3nH46v9bhuRqUkBKaX2CG17CZ859Tp 4E/ALiZN7wSoQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m9OuO-006qwF-MH; Fri, 30 Jul 2021 11:34:24 +0200 From: Mauro Carvalho Chehab To: Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Rob Herring , Vinod Koul , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 4/4] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Date: Fri, 30 Jul 2021 11:34:21 +0200 Message-Id: <1e9669ef81f523f4e16f10d8c720507dea3dc444.1627637448.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the bindings for HiKey 970 (hi3670) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml new file mode 100644 index 000000000000..1e0153e4f4a5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin970 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi970-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + phy-supply: + description: The PCIe PHY power supply + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: phy_ref + - const: aux + - const: apb_phy + - const: apb_sys + - const: aclk + + clkreq-gpios: + description: Clock request GPIOs + maxItems: 3 + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Eye diagram for phy. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - hisilicon,eye-diagram-param + - phy-supply + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + #phy-cells = <0>; + phy-supply = <&ldo33>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", "aclk"; + hisilicon,eye-diagram-param = <0xffffffff 0xffffffff + 0xffffffff 0xffffffff 0xffffffff>; + }; + };