| Message ID | 1698202408-14608-2-git-send-email-quic_taozha@quicinc.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [v2,1/8] dt-bindings: arm: Add support for CMB element size | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | fail | build log |
On Wed, Oct 25, 2023 at 10:53:21AM +0800, Tao Zhang wrote: > Add property "qcom,cmb-elem-size" to support CMB(Continuous > Multi-Bit) element for TPDM. The associated aggregator will read > this size before it is enabled. CMB element size currently only > supports 32-bit and 64-bit. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> > --- > .../bindings/arm/qcom,coresight-tpdm.yaml | 27 ++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > index 61ddc3b..f9a2025 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > @@ -52,6 +52,14 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint8 > enum: [32, 64] > > + qcom,cmb-element-size: What are the units? Use '-bits' suffix. > + description: > + Specifies the CMB(Continuous Multi-Bit) element size supported by > + the monitor. The associated aggregator will read this size before it > + is enabled. CMB element size currently only supports 32-bit and 64-bit. The enum says 8-bit is supported. > + $ref: /schemas/types.yaml#/definitions/uint8 > + enum: [8, 32, 64] > + > qcom,dsb-msrs-num: > description: > Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) > @@ -110,4 +118,23 @@ examples: > }; > }; > > + tpdm@6c29000 { > + compatible = "qcom,coresight-tpdm", "arm,primecell"; > + reg = <0x06c29000 0x1000>; > + reg-names = "tpdm-base"; > + > + qcom,cmb-element-size = /bits/ 8 <64>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + tpdm_ipcc_out_funnel_center: endpoint { > + remote-endpoint = > + <&funnel_center_in_tpdm_ipcc>; > + }; > + }; > + }; > + }; > ... > -- > 2.7.4 >
On 10/27/2023 5:25 AM, Rob Herring wrote: > On Wed, Oct 25, 2023 at 10:53:21AM +0800, Tao Zhang wrote: >> Add property "qcom,cmb-elem-size" to support CMB(Continuous >> Multi-Bit) element for TPDM. The associated aggregator will read >> this size before it is enabled. CMB element size currently only >> supports 32-bit and 64-bit. >> >> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> >> --- >> .../bindings/arm/qcom,coresight-tpdm.yaml | 27 ++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> index 61ddc3b..f9a2025 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> @@ -52,6 +52,14 @@ properties: >> $ref: /schemas/types.yaml#/definitions/uint8 >> enum: [32, 64] >> >> + qcom,cmb-element-size: > What are the units? Use '-bits' suffix. Yes, its unit should be bit. Do you mean that you prefer to use "qcom, cmb-element-size-bits"? Do I also need to replace "qcom, dsb-element-size" with "qcom, dsb-element-size-bits". > >> + description: >> + Specifies the CMB(Continuous Multi-Bit) element size supported by >> + the monitor. The associated aggregator will read this size before it >> + is enabled. CMB element size currently only supports 32-bit and 64-bit. > The enum says 8-bit is supported. Yes, 8-bit is supported. I will update the description in the next patch series. Best, Tao > >> + $ref: /schemas/types.yaml#/definitions/uint8 >> + enum: [8, 32, 64] >> + >> qcom,dsb-msrs-num: >> description: >> Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) >> @@ -110,4 +118,23 @@ examples: >> }; >> }; >> >> + tpdm@6c29000 { >> + compatible = "qcom,coresight-tpdm", "arm,primecell"; >> + reg = <0x06c29000 0x1000>; >> + reg-names = "tpdm-base"; >> + >> + qcom,cmb-element-size = /bits/ 8 <64>; >> + >> + clocks = <&aoss_qmp>; >> + clock-names = "apb_pclk"; >> + >> + out-ports { >> + port { >> + tpdm_ipcc_out_funnel_center: endpoint { >> + remote-endpoint = >> + <&funnel_center_in_tpdm_ipcc>; >> + }; >> + }; >> + }; >> + }; >> ... >> -- >> 2.7.4 >>
On 11/1/2023 2:29 PM, Tao Zhang wrote: > > On 10/27/2023 5:25 AM, Rob Herring wrote: >> On Wed, Oct 25, 2023 at 10:53:21AM +0800, Tao Zhang wrote: >>> Add property "qcom,cmb-elem-size" to support CMB(Continuous >>> Multi-Bit) element for TPDM. The associated aggregator will read >>> this size before it is enabled. CMB element size currently only >>> supports 32-bit and 64-bit. >>> >>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> >>> --- >>> .../bindings/arm/qcom,coresight-tpdm.yaml | 27 >>> ++++++++++++++++++++++ >>> 1 file changed, 27 insertions(+) >>> >>> diff --git >>> a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >>> b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >>> index 61ddc3b..f9a2025 100644 >>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >>> @@ -52,6 +52,14 @@ properties: >>> $ref: /schemas/types.yaml#/definitions/uint8 >>> enum: [32, 64] >>> + qcom,cmb-element-size: >> What are the units? Use '-bits' suffix. > > Yes, its unit should be bit. > > Do you mean that you prefer to use "qcom, cmb-element-size-bits"? > > Do I also need to replace "qcom, dsb-element-size" with "qcom, > dsb-element-size-bits". I will continue to use the property name "qcom, cmb-element-size" in order to be consistent with "qcom, dsb-element-size". Let me know if you have any concerns about this. Best, Tao > >> >>> + description: >>> + Specifies the CMB(Continuous Multi-Bit) element size >>> supported by >>> + the monitor. The associated aggregator will read this size >>> before it >>> + is enabled. CMB element size currently only supports 32-bit >>> and 64-bit. >> The enum says 8-bit is supported. > > Yes, 8-bit is supported. I will update the description in the next > patch series. > > > Best, > > Tao > >> >>> + $ref: /schemas/types.yaml#/definitions/uint8 >>> + enum: [8, 32, 64] >>> + >>> qcom,dsb-msrs-num: >>> description: >>> Specifies the number of DSB(Discrete Single Bit) MSR(mux >>> select register) >>> @@ -110,4 +118,23 @@ examples: >>> }; >>> }; >>> + tpdm@6c29000 { >>> + compatible = "qcom,coresight-tpdm", "arm,primecell"; >>> + reg = <0x06c29000 0x1000>; >>> + reg-names = "tpdm-base"; >>> + >>> + qcom,cmb-element-size = /bits/ 8 <64>; >>> + >>> + clocks = <&aoss_qmp>; >>> + clock-names = "apb_pclk"; >>> + >>> + out-ports { >>> + port { >>> + tpdm_ipcc_out_funnel_center: endpoint { >>> + remote-endpoint = >>> + <&funnel_center_in_tpdm_ipcc>; >>> + }; >>> + }; >>> + }; >>> + }; >>> ... >>> -- >>> 2.7.4 >>> > _______________________________________________ > CoreSight mailing list -- coresight@lists.linaro.org > To unsubscribe send an email to coresight-leave@lists.linaro.org
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 61ddc3b..f9a2025 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -52,6 +52,14 @@ properties: $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64] + qcom,cmb-element-size: + description: + Specifies the CMB(Continuous Multi-Bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. CMB element size currently only supports 32-bit and 64-bit. + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [8, 32, 64] + qcom,dsb-msrs-num: description: Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) @@ -110,4 +118,23 @@ examples: }; }; + tpdm@6c29000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x06c29000 0x1000>; + reg-names = "tpdm-base"; + + qcom,cmb-element-size = /bits/ 8 <64>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_out_funnel_center: endpoint { + remote-endpoint = + <&funnel_center_in_tpdm_ipcc>; + }; + }; + }; + }; ...