| Message ID | 1675049539-14976-2-git-send-email-hongxing.zhu@nxp.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add i.MX PCIe EP mode support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | fail | build log |
On Mon, Jan 30, 2023 at 11:32:15AM +0800, Richard Zhu wrote: > Prepare to create one separate DT-schema for i.MX PCIe Endpoint > controllers in another commit. This and patch 2 should be 1 commit. It is 1 logical change. With only this commit, fsl,imx8m*-pcie-ep becomes undocumented. Rob
> -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: 2023年1月31日 6:31 > To: Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: krzysztof.kozlowski+dt@linaro.org; l.stach@pengutronix.de; > shawnguo@kernel.org; lorenzo.pieralisi@arm.com; Peng Fan > <peng.fan@nxp.com>; marex@denx.de; Marcel Ziswiler > <marcel.ziswiler@toradex.com>; tharvey@gateworks.com; Frank Li > <frank.li@nxp.com>; devicetree@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [PATCH v7 1/5] dt-bindings: imx6q-pcie: Prepare to separate the > Endpoint binding document > > On Mon, Jan 30, 2023 at 11:32:15AM +0800, Richard Zhu wrote: > > Prepare to create one separate DT-schema for i.MX PCIe Endpoint > > controllers in another commit. > > This and patch 2 should be 1 commit. It is 1 logical change. With only this > commit, fsl,imx8m*-pcie-ep becomes undocumented. Okay, would merge these two commits into one. Thanks. Best Regards Richard Zhu > > Rob
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index f13f87fddb3d..2985d14b9ecc 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -13,6 +13,11 @@ maintainers: description: |+ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. + The controller instances are dual mode where in they can work either in + Root Port mode or Endpoint mode but one at a time. + + See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree + bindings. properties: compatible: @@ -24,9 +29,6 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie - - fsl,imx8mm-pcie-ep - - fsl,imx8mq-pcie-ep - - fsl,imx8mp-pcie-ep reg: items: @@ -178,6 +180,7 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# + - if: properties: compatible:
Prepare to create one separate DT-schema for i.MX PCIe Endpoint controllers in another commit. Remove the EP mode compatible, and update the description. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)