| Message ID | 1627581885-32165-2-git-send-email-sibis@codeaurora.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Fixup register offsets to support per core L3 DCVS | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Thu, 29 Jul 2021 23:34:42 +0530, Sibi Sankar wrote: > Re-arranging the register regions to support per core L3 DCVS would lead > to bindings breakage when using an older dt with a newer kernel. So, > document the EPSS compatible for SM8250/SM8350 SoCs and use them in the > CPUFreq-hw driver to prevent such breakages. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > --- > Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
Quoting Sibi Sankar (2021-07-29 11:04:42) > Re-arranging the register regions to support per core L3 DCVS would lead > to bindings breakage when using an older dt with a newer kernel. So, > document the EPSS compatible for SM8250/SM8350 SoCs and use them in the > CPUFreq-hw driver to prevent such breakages. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt index 9299028ee712..ee52fd8d3c9a 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt @@ -8,7 +8,11 @@ Properties: - compatible Usage: required Value type: <string> - Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss". + Definition: must be one of: + "qcom,cpufreq-epss" + "qcom,cpufreq-hw" + "qcom,sm8250-cpufreq-epss" + "qcom,sm8350-cpufreq-epss" - clocks Usage: required
Re-arranging the register regions to support per core L3 DCVS would lead to bindings breakage when using an older dt with a newer kernel. So, document the EPSS compatible for SM8250/SM8350 SoCs and use them in the CPUFreq-hw driver to prevent such breakages. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)