From patchwork Sat Mar 13 18:00:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hsin-Hsiung Wang X-Patchwork-Id: 1452529 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DyVqv2kZNz9sRf for ; Sun, 14 Mar 2021 05:01:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234251AbhCMSBM (ORCPT ); Sat, 13 Mar 2021 13:01:12 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:48742 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234244AbhCMSBH (ORCPT ); Sat, 13 Mar 2021 13:01:07 -0500 X-UUID: 68d85f61837c494685505281942eaee7-20210314 X-UUID: 68d85f61837c494685505281942eaee7-20210314 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 297667531; Sun, 14 Mar 2021 02:01:01 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 14 Mar 2021 02:00:59 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 14 Mar 2021 02:00:59 +0800 From: Hsin-Hsiung Wang To: Stephen Boyd , Rob Herring , Matthias Brugger CC: Hsin-Hsiung Wang , , , , , , Subject: [PATCH v7 2/4] dt-bindings: spmi: document binding for the Mediatek SPMI controller Date: Sun, 14 Mar 2021 02:00:51 +0800 Message-ID: <1615658453-3989-3-git-send-email-hsin-hsiung.wang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1615658453-3989-1-git-send-email-hsin-hsiung.wang@mediatek.com> References: <1615658453-3989-1-git-send-email-hsin-hsiung.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds documentation for the SPMI controller found on Mediatek SoCs. Signed-off-by: Hsin-Hsiung Wang Reviewed-by: Rob Herring --- changes since v6: - no changes. --- .../bindings/spmi/mtk,spmi-mtk-pmif.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml new file mode 100644 index 000000000000..a43b0302d503 --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek SPMI Controller Device Tree Bindings + +maintainers: + - Hsin-Hsiung Wang + +description: |+ + On MediaTek SoCs the PMIC is connected via SPMI and the controller allows + for multiple SoCs to control a single SPMI master. + +allOf: + - $ref: "spmi.yaml" + +properties: + compatible: + const: mediatek,mt6873-spmi + + reg: + maxItems: 2 + + reg-names: + items: + - const: pmif + - const: spmimst + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: pmif_sys_ck + - const: pmif_tmr_ck + - const: spmimst_clk_mux + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; +...