| Message ID | 1606714984-16593-1-git-send-email-yash.shah@sifive.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [v2,1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | success |
On Mon, Nov 30, 2020 at 11:13:03AM +0530, Yash Shah wrote: > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > compared to 3 in FU540. Update the DT documentation accordingly with > "compatible" and "interrupt" property changes. 'dt-bindings: riscv: ...' for the subject. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > Changes in v2: > - Changes as per Rob Herring's request on v1 > --- > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 35 ++++++++++++++++++++-- > 1 file changed, 32 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > index efc0198..749265c 100644 > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > @@ -27,6 +27,7 @@ select: > items: > - enum: > - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > > required: > - compatible > @@ -34,7 +35,9 @@ select: > properties: > compatible: > items: > - - const: sifive,fu540-c000-ccache > + - enum: > + - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > - const: cache > > cache-block-size: > @@ -53,9 +56,15 @@ properties: > > interrupts: > description: | > - Must contain entries for DirError, DataError and DataFail signals. > + Must contain 3 entries for FU540 (DirError, DataError and DataFail) or 4 > + entries for other chips (DirError, DirFail, DataError, DataFail signals) While below is wrong, don't give descriptions that just repeat what the schema says. > minItems: 3 > - maxItems: 3 > + maxItems: 4 > + items: > + - description: DirError interrupt > + - description: DirFail interrupt > + - description: DataError interrupt > + - description: DataFail interrupt This says DataFail is optional. > > reg: > maxItems: 1 > @@ -67,6 +76,26 @@ properties: > The reference to the reserved-memory for the L2 Loosely Integrated Memory region. > The reserved memory node should be defined as per the bindings in reserved-memory.txt. > > +if: > + properties: > + compatible: > + contains: > + const: sifive,fu540-c000-ccache > + > +then: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError and DataFail signals. > + maxItems: 3 > + > +else: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DirFail, DataError, DataFail signals. > + minItems: 4 > + > additionalProperties: false > > required: > -- > 2.7.4 >
> -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: 09 December 2020 04:52 > To: Yash Shah <yash.shah@openfive.com> > Cc: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org; > devicetree@vger.kernel.org; bp@suse.de; anup@brainfault.org; > Jonathan.Cameron@huawei.com; wsa@kernel.org; sam@ravnborg.org; > aou@eecs.berkeley.edu; palmer@dabbelt.com; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; Sagar Kadam <sagar.kadam@openfive.com>; > Sachin Ghadi <sachin.ghadi@openfive.com> > Subject: Re: [PATCH v2 1/2] RISC-V: Update l2 cache DT documentation to > add support for SiFive FU740 > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Mon, Nov 30, 2020 at 11:13:03AM +0530, Yash Shah wrote: > > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > > compared to 3 in FU540. Update the DT documentation accordingly with > > "compatible" and "interrupt" property changes. > > 'dt-bindings: riscv: ...' for the subject. > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > --- > > Changes in v2: > > - Changes as per Rob Herring's request on v1 > > --- > > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 35 > > ++++++++++++++++++++-- > > 1 file changed, 32 insertions(+), 3 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > index efc0198..749265c 100644 > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > @@ -27,6 +27,7 @@ select: > > items: > > - enum: > > - sifive,fu540-c000-ccache > > + - sifive,fu740-c000-ccache > > > > required: > > - compatible > > @@ -34,7 +35,9 @@ select: > > properties: > > compatible: > > items: > > - - const: sifive,fu540-c000-ccache > > + - enum: > > + - sifive,fu540-c000-ccache > > + - sifive,fu740-c000-ccache > > - const: cache > > > > cache-block-size: > > @@ -53,9 +56,15 @@ properties: > > > > interrupts: > > description: | > > - Must contain entries for DirError, DataError and DataFail signals. > > + Must contain 3 entries for FU540 (DirError, DataError and DataFail) or > 4 > > + entries for other chips (DirError, DirFail, DataError, DataFail > > + signals) > > While below is wrong, don't give descriptions that just repeat what the > schema says. Ok will remove the above description. > > > minItems: 3 > > - maxItems: 3 > > + maxItems: 4 > > + items: > > + - description: DirError interrupt > > + - description: DirFail interrupt > > + - description: DataError interrupt > > + - description: DataFail interrupt > > This says DataFail is optional. I will move back to your initial suggestion to add the new entry "DirFail" as the last index to keep the order same. Will make the corresponding changes in the driver and send a v3 patch. Thanks for your review. - Yash
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index efc0198..749265c 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -27,6 +27,7 @@ select: items: - enum: - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache required: - compatible @@ -34,7 +35,9 @@ select: properties: compatible: items: - - const: sifive,fu540-c000-ccache + - enum: + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache - const: cache cache-block-size: @@ -53,9 +56,15 @@ properties: interrupts: description: | - Must contain entries for DirError, DataError and DataFail signals. + Must contain 3 entries for FU540 (DirError, DataError and DataFail) or 4 + entries for other chips (DirError, DirFail, DataError, DataFail signals) minItems: 3 - maxItems: 3 + maxItems: 4 + items: + - description: DirError interrupt + - description: DirFail interrupt + - description: DataError interrupt + - description: DataFail interrupt reg: maxItems: 1 @@ -67,6 +76,26 @@ properties: The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. +if: + properties: + compatible: + contains: + const: sifive,fu540-c000-ccache + +then: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError and DataFail signals. + maxItems: 3 + +else: + properties: + interrupts: + description: | + Must contain entries for DirError, DirFail, DataError, DataFail signals. + minItems: 4 + additionalProperties: false required:
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the DT documentation accordingly with "compatible" and "interrupt" property changes. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- Changes in v2: - Changes as per Rob Herring's request on v1 --- .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 35 ++++++++++++++++++++-- 1 file changed, 32 insertions(+), 3 deletions(-)