From patchwork Fri Oct 2 07:35:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmlheGluIFl1ICjkv57lrrbpkasp?= X-Patchwork-Id: 1375582 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=Q3mPNlX7; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C2hcX57kBz9sSs for ; Fri, 2 Oct 2020 17:35:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726029AbgJBHfz (ORCPT ); Fri, 2 Oct 2020 03:35:55 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:53030 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725961AbgJBHfz (ORCPT ); Fri, 2 Oct 2020 03:35:55 -0400 X-UUID: 87c132f564574332a879acfb1f470b4d-20201002 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nj/HQeeWysvsdflYN4/vv8Sy4EbCpZBoM/GKszwlsR8=; b=Q3mPNlX7LbJzCGMMhr2kMLs+nOgcmLgDW6RoBbLw2iKT0JsnT6Rfy4yyCO2wnJQhCPDX3nOToW2A9aJdIo0IrgkkVMM5Ze9zZeGgFAKNIsz0+RUzHfE6BaZcUnkeGsHsxZV9+0C6zd/yLhPM2FdCsDa3K3H9WMtTLmpEo2/WeVw=; X-UUID: 87c132f564574332a879acfb1f470b4d-20201002 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 827953107; Fri, 02 Oct 2020 15:35:48 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 2 Oct 2020 15:35:46 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 2 Oct 2020 15:35:45 +0800 From: Jiaxin Yu To: , , , , , , , , , CC: , , , Jiaxin Yu Subject: [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document Date: Fri, 2 Oct 2020 15:35:40 +0800 Message-ID: <1601624142-18991-4-git-send-email-jiaxin.yu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1601624142-18991-1-git-send-email-jiaxin.yu@mediatek.com> References: <1601624142-18991-1-git-send-email-jiaxin.yu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds mt8192 audio afe document. Signed-off-by: Jiaxin Yu --- .../bindings/sound/mt8192-afe-pcm.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml new file mode 100644 index 0000000000000..43852315f1867 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek AFE PCM controller for mt8192 + +maintainers: + - Jiaxin Yu + - Shane Chien + +properties: + compatible: + contains: + const: mediatek,mt8192-audio + + interrupts: + maxItems: 1 + description: AFE interrupt line + + resets: + maxItems: 1 + + reset-names: + const: audiosys + + apmixedsys: + maxItems: 1 + description: The mediatek apmixedsys controller + + infracfg: + maxItems: 1 + description: The mediatek infracfg controller + + topckgen: + maxItems: 1 + description: The mediatek topckgen controller + + power-domains: + maxItems: 1 + + clocks: + items: + - description: AFE clock + - description: ADDA DAC clock + - description: ADDA DAC pre-distortion clock + - description: audio infra sys clock + - description: audio infra 26M clock + + clock-names: + items: + - const: aud_afe_clk + - const: aud_dac_clk + - const: aud_dac_predis_clk + - const: aud_infra_clk + - const: aud_infra_26m_clk + +required: + - compatible + - interrupts + - resets + - reset-names + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + afe: mt8192-afe-pcm { + compatible = "mediatek,mt8192-audio"; + interrupts = ; + resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + apmixedsys = <&apmixedsys>; + infracfg = <&infracfg>; + topckgen = <&topckgen>; + power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>; + clocks = <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_DAC>, + <&audsys CLK_AUD_DAC_PREDIS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_B>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_infra_clk", + "aud_infra_26m_clk"; + }; + +...