| Message ID | 1568047940-14490-2-git-send-email-vitaly.gaiduk@cloudbear.ru |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | [v3,1/2] net: phy: dp83867: Add documentation for SGMII mode type | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On 9/9/19 9:52 AM, Vitaly Gaiduk wrote: > Add documentation of ti,sgmii-ref-clock-output-enable > which can be used to select SGMII mode type (4 or 6-wire). > > Signed-off-by: Vitaly Gaiduk <vitaly.gaiduk@cloudbear.ru> > --- > Documentation/devicetree/bindings/net/ti,dp83867.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt > index db6aa3f..c98c682 100644 > --- a/Documentation/devicetree/bindings/net/ti,dp83867.txt > +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt > @@ -37,6 +37,10 @@ Optional property: > for applicable values. The CLK_OUT pin can also > be disabled by this property. When omitted, the > PHY's default will be left as is. > + - ti,sgmii-ref-clock-output-enable - This denotes the fact which > + SGMII configuration is used (4 or 6-wire modes). > + Some MACs work with differential SGMII clock. > + See data manual for details. The wording is a bit odd here, I would just omit "the fact" to make the sentence more readable. With that: Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 2019-09-09 at 20:19 +0300, Vitaly Gaiduk wrote: > This patch adds ability to switch beetween two PHY SGMII modes. > Some hardware, for example, FPGA IP designs may use 6-wire mode > which enables differential SGMII clock to MAC. > > + > + val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); > + /* SGMII type is set to 4-wire mode by default. > + * If we place appropriate property in dts (see above) > + * switch on 6-wire mode. > + */ > + if (dp83867->sgmii_ref_clk_en) > + val |= DP83867_SGMII_TYPE; > + else > + val &= ~DP83867_SGMII_TYPE; > + phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); Should use phy_modify_mmd().
From: Vitaly Gaiduk <vitaly.gaiduk@cloudbear.ru> Date: Mon, 9 Sep 2019 20:19:24 +0300 > This patch adds ability to switch beetween two PHY SGMII modes. > Some hardware, for example, FPGA IP designs may use 6-wire mode > which enables differential SGMII clock to MAC. > > Signed-off-by: Vitaly Gaiduk <vitaly.gaiduk@cloudbear.ru> Applied.
Hello, David. Should I patch commit as Trent Piepho suggested? He wrote about using phy_modify_mmd() instead. Vitaly. On 12.09.2019 1:37, David Miller wrote: > From: Vitaly Gaiduk <vitaly.gaiduk@cloudbear.ru> > Date: Mon, 9 Sep 2019 20:19:24 +0300 > >> This patch adds ability to switch beetween two PHY SGMII modes. >> Some hardware, for example, FPGA IP designs may use 6-wire mode >> which enables differential SGMII clock to MAC. >> >> Signed-off-by: Vitaly Gaiduk <vitaly.gaiduk@cloudbear.ru> > Applied.
diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt index db6aa3f..c98c682 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83867.txt +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt @@ -37,6 +37,10 @@ Optional property: for applicable values. The CLK_OUT pin can also be disabled by this property. When omitted, the PHY's default will be left as is. + - ti,sgmii-ref-clock-output-enable - This denotes the fact which + SGMII configuration is used (4 or 6-wire modes). + Some MACs work with differential SGMII clock. + See data manual for details. Note: ti,min-output-impedance and ti,max-output-impedance are mutually exclusive. When both properties are present ti,max-output-impedance
Add documentation of ti,sgmii-ref-clock-output-enable which can be used to select SGMII mode type (4 or 6-wire). Signed-off-by: Vitaly Gaiduk <vitaly.gaiduk@cloudbear.ru> --- Documentation/devicetree/bindings/net/ti,dp83867.txt | 4 ++++ 1 file changed, 4 insertions(+)