| Message ID | 1536131342-28041-3-git-send-email-nava.manne@xilinx.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add reset driver support for ZynqMP | expand |
Hi, On Wed, 2018-09-05 at 12:39 +0530, Nava kishore Manne wrote: > Add documentation to describe Xilinx ZynqMP reset driver > bindings. > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> > --- > Changes for v3: > -Corrected Commit Msg. > Changes for v2: > -Moved reset node as a child to firwmare > node. > > .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 142 +++++++++++++++++++++ > 1 file changed, 142 insertions(+) > > diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt > index 1b431d9..351b1bb 100644 > --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt [...] > ------- > Example > ------- > @@ -25,5 +163,9 @@ firmware { > zynqmp_firmware: zynqmp-firmware { > compatible = "xlnx,zynqmp-firmware"; > method = "smc"; > + reset-controller:reset-controller@0 { I think the label should use underscore instead of hyphen, and the unit address part should be removed from the node name. There is no unit address, as there is no reg property inside the node and the parent node doesn't have #address-cells: reset_controller: reset-controller { > + compatible = "xlnx,zynqmp-reset"; > + #reset-cells = <1>; > + }; > }; > }; regards Philipp
Hi Philipp Thanks for the quick response.. Please find my commnets inline. > -----Original Message----- > From: Philipp Zabel [mailto:p.zabel@pengutronix.de] > Sent: Wednesday, September 5, 2018 3:40 PM > To: Nava kishore Manne <navam@xilinx.com>; robh+dt@kernel.org; > mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja > <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: Re: [RFC PATCH v3 2/3] dt-bindings: reset: Add bindings for ZynqMP > reset driver > > Hi, > > On Wed, 2018-09-05 at 12:39 +0530, Nava kishore Manne wrote: > > Add documentation to describe Xilinx ZynqMP reset driver bindings. > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> > > --- > > Changes for v3: > > -Corrected Commit Msg. > > Changes for v2: > > -Moved reset node as a child to firwmare > > node. > > > > .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 142 > +++++++++++++++++++++ > > 1 file changed, 142 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmwa > > re.txt > > b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmwa > > re.txt > > index 1b431d9..351b1bb 100644 > > --- > > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmwa > > re.txt > > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi > > +++ rmware.txt > [...] > > ------- > > Example > > ------- > > @@ -25,5 +163,9 @@ firmware { > > zynqmp_firmware: zynqmp-firmware { > > compatible = "xlnx,zynqmp-firmware"; > > method = "smc"; > > + reset-controller:reset-controller@0 { > > I think the label should use underscore instead of hyphen, and the unit address > part should be removed from the node name. There is no unit address, as there > is no reg property inside the node and the parent node doesn't have #address- > cells: > Will fix in the next version. Regards, Navakishore.
On Wed, Sep 05, 2018 at 12:39:01PM +0530, Nava kishore Manne wrote: > Add documentation to describe Xilinx ZynqMP reset driver > bindings. > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> > --- > Changes for v3: > -Corrected Commit Msg. > Changes for v2: > -Moved reset node as a child to firwmare > node. Why? There's no reason for that. The parent can be multiple providers. You only need child nodes if the sub functions have their own DT resources. > > .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 142 +++++++++++++++++++++ > 1 file changed, 142 insertions(+) > > diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt > index 1b431d9..351b1bb 100644 > --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt > @@ -17,6 +17,144 @@ Required properties: > - "smc" : SMC #0, following the SMCCC > - "hvc" : HVC #0, following the SMCCC > > +-------------------------------------------------------------------------- > + = Zynq UltraScale+ MPSoC reset driver binding = > +-------------------------------------------------------------------------- > +The Zynq UltraScale+ MPSoC has several different resets. > + > +See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information > +about zynqmp resets. > + > +Please also refer to reset.txt in this directory for common reset > +controller binding usage. > + > +Required Properties: > +- compatible: "xlnx,zynqmp-reset" > +- #reset-cells: Specifies the number of cells needed to encode reset > + line, should be 1 > + > +Reset outputs: > + 0 :PCIE config reset. > + 1 :PCIE bridge block level reset (AXI interface). > + 2 :PCIE control block level,reset. > + 3 :Display Port block level reset (includes DPDMA). > + 4 :FPD WDT reset. > + 5 :AF_FM5 block level reset. > + 6 :AF_FM4 block level reset. > + 7 :AF_FM3 block level reset. > + 8 :AF_FM2 block level reset. > + 9 :AF_FM1 block level reset. > + 10 :AF_FM0 block level reset. > + 11 :GDMA block level reset. > + 12 :Pixel Processor (GPU_PP1) block level reset. > + 13 :Pixel Processor (GPU_PP0) block level reset. > + 14 :GPU block level reset. > + 15 :GT block level reset. > + 16 :Sata block level reset. > + 17 :ACPU3 power on reset. > + 18 :ACPU2 power on reset. > + 19 :ACPU1 power on reset. > + 20 :ACPU0 power on reset. > + 21 :APU L2 reset. > + 22 :ACPU3 reset. > + 23 :ACPU2 reset. > + 24 :ACPU1 reset. > + 25 :ACPU0 reset. > + 26 :DDR block level reset inside of the DDR Sub System. > + 27 :APM block level reset inside of the DDR Sub System. > + 28 :soft reset. > + 29 :GEM 0 reset. > + 30 :GEM 1 reset. > + 31 :GEM 2 reset. > + 32 :GEM 3 reset. > + 33 :qspi reset. > + 34 :uart0 reset. > + 35 :uart1 reset. > + 36 :spi0 reset. > + 37 :spi1 reset. > + 38 :sdio0 reset. > + 39 :sdio1 reset. > + 40 :can0 reset. > + 41 :can1 reset. > + 42 :i2c0 reset. > + 43 :i2c1 reset. > + 44 :ttc0 reset. > + 45 :ttc1 reset. > + 46 :ttc2 reset. > + 47 :ttc3 reset. > + 48 :swdt reset. > + 49 :nand reset. > + 50 :adma reset. > + 51 :gpio reset. > + 52 :iou_cc reset. > + 53 :timestamp reset. > + 54 :rpu_r50 reset. > + 55 :rpu r51 reset. > + 56 :rpu_amba reset. > + 57 :ocm reset. > + 58 :rpu_pge reset. > + 59 :usb0_core reset. > + 60 :usb1_core reset. > + 61 :usb0_hiber reset. > + 62 :usb1_hiber reset. > + 63 :usb0_apb reset. > + 64 :usb1_apb reset. > + 65 :ipi reset. > + 66 :apm reset. > + 67 :rtc reset. > + 68 :sysmon reset. > + 69 :afi_fm6 reset. > + 70 :lpd_swdt reset. > + 71 :fpd_reset. > + 72 :rpu_dbg1 reset. > + 73 :rpu_dbg0 reset. > + 74 :dbg_lpd reset. > + 75 :dbg_fpd reset. > + 76 :apll reset. > + 77 :dpll reset. > + 78 :vpll reset. > + 79 :iopll reset. > + 80 :rpll reset. > + 81 :gpio_pl_0 reset. > + 82 :gpio_pl_1 reset. > + 83 :gpio_pl_2 reset. > + 84 :gpio_pl_3 reset. > + 85 :gpio_pl_4 reset. > + 86 :gpio_pl_5 reset. > + 87 :gpio_pl_6 reset. > + 88 :gpio_pl_7 reset. > + 89 :gpio_pl_8 reset. > + 90 :gpio_pl_9 reset. > + 91 :gpio_pl_10 reset. > + 92 :gpio_pl_11 reset. > + 93 :gpio_pl_12 reset. > + 94 :gpio_pl_13 reset. > + 95 :gpio_pl_14 reset. > + 96 :gpio_pl_15 reset. > + 97 :gpio_pl_16 reset. > + 98 :gpio_pl_17 reset. > + 99 :gpio_pl_18 reset. > + 100 :gpio_pl_19 reset. > + 101 :gpio_pl_20 reset. > + 102 :gpio_pl_21 reset. > + 103 :gpio_pl_22 reset. > + 104 :gpio_pl_23 reset. > + 105 :gpio_pl_24 reset. > + 106 :gpio_pl_25 reset. > + 107 :gpio_pl_26 reset. > + 108 :gpio_pl_27 reset. > + 109 :gpio_pl_28 reset. > + 110 :gpio_pl_29 reset. > + 111 :gpio_pl_30 reset. > + 112 :gpio_pl_31 reset. > + 113 :rpu_ls reset. > + 114 :ps_only reset. > + 115 :pl reset. > + 116 :ps_pl0 reset > + 117 :ps_pl1 reset > + 118 :ps_pl2 reset > + 119 :ps_pl3 reset > + > ------- > Example > ------- > @@ -25,5 +163,9 @@ firmware { > zynqmp_firmware: zynqmp-firmware { > compatible = "xlnx,zynqmp-firmware"; > method = "smc"; > + reset-controller:reset-controller@0 { > + compatible = "xlnx,zynqmp-reset"; > + #reset-cells = <1>; > + }; > }; > }; > -- > 2.7.4 >
Hi Rob, Thanks for providing the comments... Please find my response inline. > -----Original Message----- > From: Rob Herring [mailto:robh@kernel.org] > Sent: Tuesday, September 11, 2018 1:42 AM > To: Nava kishore Manne <navam@xilinx.com> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; > p.zabel@pengutronix.de; Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah > <JOLLYS@xilinx.com>; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: Re: [RFC PATCH v3 2/3] dt-bindings: reset: Add bindings for ZynqMP > reset driver > > On Wed, Sep 05, 2018 at 12:39:01PM +0530, Nava kishore Manne wrote: > > Add documentation to describe Xilinx ZynqMP reset driver bindings. > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> > > --- > > Changes for v3: > > -Corrected Commit Msg. > > Changes for v2: > > -Moved reset node as a child to firwmare > > node. > > Why? There's no reason for that. The parent can be multiple providers. > You only need child nodes if the sub functions have their own DT resources. > This driver having a dependency on firmware. So I have moved this node as a child to firmware As per other drivers which is using this firmware interface https://lkml.org/lkml/2018/8/14/432 I didn't get your comment could you please elaborate more??? Did you mean I should move the changes in the file to Documentation/devicetree/bindings/reset/ ??? Regards, Navakishore.
diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt index 1b431d9..351b1bb 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt @@ -17,6 +17,144 @@ Required properties: - "smc" : SMC #0, following the SMCCC - "hvc" : HVC #0, following the SMCCC +-------------------------------------------------------------------------- + = Zynq UltraScale+ MPSoC reset driver binding = +-------------------------------------------------------------------------- +The Zynq UltraScale+ MPSoC has several different resets. + +See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information +about zynqmp resets. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required Properties: +- compatible: "xlnx,zynqmp-reset" +- #reset-cells: Specifies the number of cells needed to encode reset + line, should be 1 + +Reset outputs: + 0 :PCIE config reset. + 1 :PCIE bridge block level reset (AXI interface). + 2 :PCIE control block level,reset. + 3 :Display Port block level reset (includes DPDMA). + 4 :FPD WDT reset. + 5 :AF_FM5 block level reset. + 6 :AF_FM4 block level reset. + 7 :AF_FM3 block level reset. + 8 :AF_FM2 block level reset. + 9 :AF_FM1 block level reset. + 10 :AF_FM0 block level reset. + 11 :GDMA block level reset. + 12 :Pixel Processor (GPU_PP1) block level reset. + 13 :Pixel Processor (GPU_PP0) block level reset. + 14 :GPU block level reset. + 15 :GT block level reset. + 16 :Sata block level reset. + 17 :ACPU3 power on reset. + 18 :ACPU2 power on reset. + 19 :ACPU1 power on reset. + 20 :ACPU0 power on reset. + 21 :APU L2 reset. + 22 :ACPU3 reset. + 23 :ACPU2 reset. + 24 :ACPU1 reset. + 25 :ACPU0 reset. + 26 :DDR block level reset inside of the DDR Sub System. + 27 :APM block level reset inside of the DDR Sub System. + 28 :soft reset. + 29 :GEM 0 reset. + 30 :GEM 1 reset. + 31 :GEM 2 reset. + 32 :GEM 3 reset. + 33 :qspi reset. + 34 :uart0 reset. + 35 :uart1 reset. + 36 :spi0 reset. + 37 :spi1 reset. + 38 :sdio0 reset. + 39 :sdio1 reset. + 40 :can0 reset. + 41 :can1 reset. + 42 :i2c0 reset. + 43 :i2c1 reset. + 44 :ttc0 reset. + 45 :ttc1 reset. + 46 :ttc2 reset. + 47 :ttc3 reset. + 48 :swdt reset. + 49 :nand reset. + 50 :adma reset. + 51 :gpio reset. + 52 :iou_cc reset. + 53 :timestamp reset. + 54 :rpu_r50 reset. + 55 :rpu r51 reset. + 56 :rpu_amba reset. + 57 :ocm reset. + 58 :rpu_pge reset. + 59 :usb0_core reset. + 60 :usb1_core reset. + 61 :usb0_hiber reset. + 62 :usb1_hiber reset. + 63 :usb0_apb reset. + 64 :usb1_apb reset. + 65 :ipi reset. + 66 :apm reset. + 67 :rtc reset. + 68 :sysmon reset. + 69 :afi_fm6 reset. + 70 :lpd_swdt reset. + 71 :fpd_reset. + 72 :rpu_dbg1 reset. + 73 :rpu_dbg0 reset. + 74 :dbg_lpd reset. + 75 :dbg_fpd reset. + 76 :apll reset. + 77 :dpll reset. + 78 :vpll reset. + 79 :iopll reset. + 80 :rpll reset. + 81 :gpio_pl_0 reset. + 82 :gpio_pl_1 reset. + 83 :gpio_pl_2 reset. + 84 :gpio_pl_3 reset. + 85 :gpio_pl_4 reset. + 86 :gpio_pl_5 reset. + 87 :gpio_pl_6 reset. + 88 :gpio_pl_7 reset. + 89 :gpio_pl_8 reset. + 90 :gpio_pl_9 reset. + 91 :gpio_pl_10 reset. + 92 :gpio_pl_11 reset. + 93 :gpio_pl_12 reset. + 94 :gpio_pl_13 reset. + 95 :gpio_pl_14 reset. + 96 :gpio_pl_15 reset. + 97 :gpio_pl_16 reset. + 98 :gpio_pl_17 reset. + 99 :gpio_pl_18 reset. + 100 :gpio_pl_19 reset. + 101 :gpio_pl_20 reset. + 102 :gpio_pl_21 reset. + 103 :gpio_pl_22 reset. + 104 :gpio_pl_23 reset. + 105 :gpio_pl_24 reset. + 106 :gpio_pl_25 reset. + 107 :gpio_pl_26 reset. + 108 :gpio_pl_27 reset. + 109 :gpio_pl_28 reset. + 110 :gpio_pl_29 reset. + 111 :gpio_pl_30 reset. + 112 :gpio_pl_31 reset. + 113 :rpu_ls reset. + 114 :ps_only reset. + 115 :pl reset. + 116 :ps_pl0 reset + 117 :ps_pl1 reset + 118 :ps_pl2 reset + 119 :ps_pl3 reset + ------- Example ------- @@ -25,5 +163,9 @@ firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; method = "smc"; + reset-controller:reset-controller@0 { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; }; };
Add documentation to describe Xilinx ZynqMP reset driver bindings. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> --- Changes for v3: -Corrected Commit Msg. Changes for v2: -Moved reset node as a child to firwmare node. .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 142 +++++++++++++++++++++ 1 file changed, 142 insertions(+)