From patchwork Wed May 23 07:42:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lin Huang X-Patchwork-Id: 918803 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40rPdr6hLBz9s2S for ; Wed, 23 May 2018 17:43:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932104AbeEWHmv (ORCPT ); Wed, 23 May 2018 03:42:51 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:36415 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932102AbeEWHms (ORCPT ); Wed, 23 May 2018 03:42:48 -0400 Received: by mail-pl0-f65.google.com with SMTP id v24-v6so12507121plo.3; Wed, 23 May 2018 00:42:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qhCrE419nVKe9w71RORaZgvzgDwybSgWWnnbiC4ouK0=; b=BiDDP9TkkL3Ep2nSfaqiJ6tpF16NzKa578cdRHLcOjyYcLFaIOoa7MFSWW0wcfo9xf CEGKIZo1hMYaP5gZWc5C9WoY9vum8OIvBtvXxB3uGRBqy0ZdNZWmk/rrKOw0KF2vDU7K XgVXyjVwr4q0DhOA8cOxZGUxrbP2VKxoWi0v/JB4YEpuMlVZjIQXnHKNigyatfSK0A/W LbXIuUZYZchTR+6KhZfABugMeOw8TRQdYQexpfHOuZ791wSSq9Dd/9I0ksb+eGxYLTYR rXZZA56/GuSwotTCV9TExLh7INOayS8UmxKKhcrlZax7k4uj9YUkyeAD8sQl3hcYvCDV o6gw== X-Gm-Message-State: ALKqPwea6dZrQjEH5BLmsLC4BKR8aNz/8bhUiCnR7+pTv+Mrl8g9Hmi5 2VAkvaoaRUo/6XaiWhGYJ/I= X-Google-Smtp-Source: AB8JxZoGbv5ziMppXtOdoa0zzp6KZN6p4dh618+FThdJ2Fknp5mygZImHV/GLfCXjvLUTa3hOHzFvQ== X-Received: by 2002:a17:902:1023:: with SMTP id b32-v6mr1828638pla.145.1527061367438; Wed, 23 May 2018 00:42:47 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j74-v6sm41139540pfk.25.2018.05.23.00.42.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 23 May 2018 00:42:46 -0700 (PDT) From: Lin Huang To: seanpaul@chromium.org, airlied@linux.ie, zyw@rock-chips.com, kishon@ti.com Cc: dianders@chromium.org, briannorris@chromium.org, linux-rockchip@lists.infradead.org, heiko@sntech.de, daniel.vetter@intel.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, eballetbo@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org, Lin Huang Subject: [PATCH v7 2/5] Documentation: dt-bindings: phy: add phy_config for Rockchip USB Type-C PHY Date: Wed, 23 May 2018 15:42:30 +0800 Message-Id: <1527061353-16902-2-git-send-email-hl@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527061353-16902-1-git-send-email-hl@rock-chips.com> References: <1527061353-16902-1-git-send-email-hl@rock-chips.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If want to do training outside DP Firmware, need phy voltage swing and pre_emphasis value. Signed-off-by: Lin Huang Reviewed-by: Rob Herring --- Changes in v2: - None Changes in v3: - modify property description and add this property to Example Changes in v4: - None Changes in v5: - None Changes in v6: - change rockchip,phy_config to rockchip,phy-config and descript it in detail. Changes in v7: - None .../devicetree/bindings/phy/phy-rockchip-typec.txt | 36 +++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt index 960da7f..40d5e7a 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt @@ -17,7 +17,11 @@ Required properties: Optional properties: - extcon : extcon specifier for the Power Delivery - + - rockchip,phy-config : A list of voltage swing(mV) and pre-emphasis + (dB) pairs. They are 3 blocks of 4 entries and + correspond to s0p0 ~ s0p3, s1p0 ~ s1p3, + s2p0 ~ s2p3, s3p0 ~ s2p3 swing and pre-emphasis + values. Required nodes : a sub-node is required for each port the phy provides. The sub-node name is used to identify dp or usb3 port, and shall be the following entries: @@ -50,6 +54,21 @@ Example: <&cru SRST_P_UPHY0_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,phy-config = <0x2a 0x00>, + <0x1f 0x15>, + <0x14 0x22>, + <0x02 0x2b>, + + <0x21 0x00>, + <0x12 0x15>, + <0x02 0x22>, + <0 0>, + + <0x15 0x00>, + <0x00 0x15>, + <0 0>, + <0 0>; + tcphy0_dp: dp-port { #phy-cells = <0>; }; @@ -74,6 +93,21 @@ Example: <&cru SRST_P_UPHY1_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,phy-config = <0x2a 0x00>, + <0x1f 0x15>, + <0x14 0x22>, + <0x02 0x2b>, + + <0x21 0x00>, + <0x12 0x15>, + <0x02 0x22>, + <0 0>, + + <0x15 0x00>, + <0x00 0x15>, + <0 0>, + <0 0>; + tcphy1_dp: dp-port { #phy-cells = <0>; };