From patchwork Mon May 14 06:20:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianguo Sun X-Patchwork-Id: 912706 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=163.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=163.com header.i=@163.com header.b="NHUpO72k"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40krF90qjhz9s0W for ; Mon, 14 May 2018 16:21:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752036AbeENGVb (ORCPT ); Mon, 14 May 2018 02:21:31 -0400 Received: from m12-11.163.com ([220.181.12.11]:48950 "EHLO m12-11.163.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751690AbeENGVX (ORCPT ); Mon, 14 May 2018 02:21:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id; bh=WVeO4+kfpbcWW5WDAu iLR5KPUth6d7/Ec0EagFGDwVI=; b=NHUpO72kbQzQRR1zHdgnOQIxpCHYvUw5Mr dWRyEaTSqfr7Va+iUf2n7vMQNJFBcJjlF/KGEXzurMggsd7Gf0cdoYbLeqIehfX0 8tc82wZfkdTBEarGaD2xqRK0LRjd31IfXLuL1RpFPBLnrxAcD4cMMCdNg//X4fh5 1Rm5UByII= Received: from localhost.localdomain (unknown [49.74.235.8]) by smtp7 (Coremail) with SMTP id C8CowAB3myu9KvlaeMF5BQ--.13241S4; Mon, 14 May 2018 14:20:49 +0800 (CST) From: sunjg79@163.com To: mathias.nyman@intel.com, gregkh@linuxfoundation.org, robh+dt@kernel.org Cc: shawn.guo@linaro.org, xuejiancheng@hisilicon.com, chunfeng.yun@mediatek.com, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, Jianguo Sun Subject: [PATCH v3 1/2] dt-bindings: usb: add bindings doc for HiSilicon STB xHCI host controller Date: Mon, 14 May 2018 14:20:41 +0800 Message-Id: <1526278842-13883-2-git-send-email-sunjg79@163.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526278842-13883-1-git-send-email-sunjg79@163.com> References: <1526278842-13883-1-git-send-email-sunjg79@163.com> X-CM-TRANSID: C8CowAB3myu9KvlaeMF5BQ--.13241S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7uF1fGw47Zw18ZrykZFWDJwb_yoW8tFykp3 y2kFW3J3WIk3W3Wa9akF10yFy3JFyrGw1rCF9rZw1UAa9xKa4FgFy2kF95ZFy7Cr1xX3yU ZF4aga47WwnFyaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jNwIDUUUUU= X-Originating-IP: [49.74.235.8] X-CM-SenderInfo: xvxqywixz6il2tof0z/1tbiRQJGsll9kKtDAAAAsv Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jianguo Sun This commit adds bindings doc for HiSilicon STB xHCI host controller. Signed-off-by: Jianguo Sun --- .../bindings/usb/hisilicon,histb-xhci.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/hisilicon,histb-xhci.txt diff --git a/Documentation/devicetree/bindings/usb/hisilicon,histb-xhci.txt b/Documentation/devicetree/bindings/usb/hisilicon,histb-xhci.txt new file mode 100644 index 0000000..f463349 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/hisilicon,histb-xhci.txt @@ -0,0 +1,45 @@ +HiSilicon STB xHCI + +The device node for HiSilicon STB xHCI host controller + +Required properties: + - compatible: should be "hisilicon,hi3798cv200-xhci" + - reg: specifies physical base address and size of the registers + - interrupts : interrupt used by the controller + - clocks: a list of phandle + clock-specifier pairs, one for each + entry in clock-names + - clock-names: must contain + "bus": for bus clock + "utmi": for utmi clock + "pipe": for pipe clock + "suspend": for suspend clock + - resets: a list of phandle and reset specifier pairs as listed in + reset-names property. + - reset-names: must contain + "soft": for soft reset + - phys: a list of phandle + phy specifier pairs + - phy-names: must contain at least one of following: + "inno": for inno phy + "combo": for combo phy + +Optional properties: + - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM + - usb3-lpm-capable: determines if platform is USB3 LPM capable + - imod-interval-ns: default interrupt moderation interval is 40000ns + +Example: + +xhci0: xchi@f98a0000 { + compatible = "hisilicon,hi3798cv200-xhci"; + reg = <0xf98a0000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_USB3_BUS_CLK>, + <&crg HISTB_USB3_UTMI_CLK>, + <&crg HISTB_USB3_PIPE_CLK>, + <&crg HISTB_USB3_SUSPEND_CLK>; + clock-names = "bus", "utmi", "pipe", "suspend"; + resets = <&crg 0xb0 12>; + reset-names = "soft"; + phys = <&usb2_phy1_port1 0>, <&combphy0 PHY_TYPE_USB3>; + phy-names = "inno", "combo"; +};