Message ID | 1523871304-48517-3-git-send-email-michel.pollet@bp.renesas.com |
---|---|
State | Not Applicable, archived |
Headers | show |
Series | Renesas RZ/N1D SMP enabler | expand |
On Mon, Apr 16, 2018 at 10:34:57AM +0100, Michel Pollet wrote: > Add a special enable method for second CA8 of the Renesas RZ/N1D > (R9A06G032). > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > --- > Documentation/devicetree/bindings/arm/cpus.txt | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 29e1dc5..b395d107 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -219,6 +219,7 @@ described below. "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" "renesas,apmu" + "renesas,r9a06g032-smp" "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp"
Add a special enable method for second CA8 of the Renesas RZ/N1D (R9A06G032). Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+)