From patchwork Thu Nov 16 12:18:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Gunda X-Patchwork-Id: 838530 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="Oai7eR+U"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="EyDamPSz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yd0gY5PDcz9s4q for ; Thu, 16 Nov 2017 23:20:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934780AbdKPMUI (ORCPT ); Thu, 16 Nov 2017 07:20:08 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:53492 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934755AbdKPMTu (ORCPT ); Thu, 16 Nov 2017 07:19:50 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 59D73607E0; Thu, 16 Nov 2017 12:19:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1510834789; bh=jaB4yLLLNA831uo8rXnMTZ9G6JFs0oxP1a7P46qrv/A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Oai7eR+UCs7wOZ6tIu+FW/hyNDYWoxP1cFDbyDqX2GvoS69TezYB/3QAoRC20M3Y6 xP2+AnP2vjWeFWwjD3uXDmD0tLcT7CaCHT9CLSoGnpE5q9vvA0SQaAMcoqxADRlmUR 6RjrX2HDJ+K/oopYqs35bg0q1OH9gAuhrYjc/w80= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from kgunda-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: kgunda@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 846816071C; Thu, 16 Nov 2017 12:19:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1510834788; bh=jaB4yLLLNA831uo8rXnMTZ9G6JFs0oxP1a7P46qrv/A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EyDamPSz3ymQsM/LfQHH9I4s6zURJ03ZgvnMXAQLn/4uU1TNbQbl9+iiKaz7zXsy8 tFg03Ruvi0rbz2a4dGrksXPNu3ZKiVrZnZO8D+BVpKbcu/vnmm4RpgyHF1PqLB6smZ 4SMdQjZnFZ6lfsq5xvbc/PjwXQec+Tm/ZuPu5Fes= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 846816071C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=kgunda@codeaurora.org From: Kiran Gunda To: bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org, Lee Jones , Daniel Thompson , Jingoo Han , Richard Purdie , Jacek Anaszewski , Pavel Machek , Rob Herring , Mark Rutland , Bartlomiej Zolnierkiewicz , linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-fbdev@vger.kernel.org Cc: linux-arm-msm-owner@vger.kernel.org, Kiran Gunda Subject: [PATCH V1 3/4] qcom: spmi-wled: Add support for OVP interrupt handling Date: Thu, 16 Nov 2017 17:48:36 +0530 Message-Id: <1510834717-21765-4-git-send-email-kgunda@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510834717-21765-1-git-send-email-kgunda@codeaurora.org> References: <1510834717-21765-1-git-send-email-kgunda@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org WLED peripheral has over voltage protection(OVP) circuitry and the OVP fault is notified through an interrupt. Though this fault condition rising is due to an incorrect hardware configuration is mitigated in the hardware, it still needs to be detected and handled. Add support for it. When WLED module is enabled, keep OVP fault interrupt disabled for 10 ms to account for soft start delay. Signed-off-by: Kiran Gunda --- .../bindings/leds/backlight/qcom-spmi-wled.txt | 7 +- drivers/video/backlight/qcom-spmi-wled.c | 83 ++++++++++++++++++++++ 2 files changed, 87 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/leds/backlight/qcom-spmi-wled.txt b/Documentation/devicetree/bindings/leds/backlight/qcom-spmi-wled.txt index 768608c..d39ee93 100644 --- a/Documentation/devicetree/bindings/leds/backlight/qcom-spmi-wled.txt +++ b/Documentation/devicetree/bindings/leds/backlight/qcom-spmi-wled.txt @@ -92,7 +92,7 @@ The PMIC is connected to the host processor via SPMI bus. Usage: optional Value type: Definition: Interrupt names associated with the interrupts. - Must be "sc-irq". + Currently supported interrupts are "sc-irq" and "ovp-irq". Example: @@ -102,8 +102,9 @@ qcom-wled@d800 { reg-names = "qcom-wled-ctrl-base", "qcom-wled-sink-base"; label = "backlight"; - interrupts = <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "sc-irq"; + interrupts = <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq", "ovp-irq"; qcom,fs-current-limit = <25000>; qcom,current-boost-limit = <970>; qcom,switching-freq = <800>; diff --git a/drivers/video/backlight/qcom-spmi-wled.c b/drivers/video/backlight/qcom-spmi-wled.c index 7dbaaa7..8b2a77a 100644 --- a/drivers/video/backlight/qcom-spmi-wled.c +++ b/drivers/video/backlight/qcom-spmi-wled.c @@ -29,9 +29,15 @@ #define QCOM_WLED_SC_DLY_MS 20 #define QCOM_WLED_SC_CNT_MAX 5 #define QCOM_WLED_SC_RESET_CNT_DLY_US 1000000 +#define QCOM_WLED_SOFT_START_DLY_US 10000 /* WLED control registers */ #define QCOM_WLED_CTRL_FAULT_STATUS 0x08 +#define QCOM_WLED_CTRL_ILIM_FAULT_BIT BIT(0) +#define QCOM_WLED_CTRL_OVP_FAULT_BIT BIT(1) +#define QCOM_WLED_CTRL_SC_FAULT_BIT BIT(2) + +#define QCOM_WLED_CTRL_INT_RT_STS 0x10 #define QCOM_WLED_CTRL_MOD_ENABLE 0x46 #define QCOM_WLED_CTRL_MOD_EN_MASK BIT(7) @@ -90,6 +96,7 @@ struct qcom_wled_config { u32 fs_current; u32 string_cfg; int sc_irq; + int ovp_irq; bool en_cabc; bool ext_pfet_sc_pro_en; }; @@ -106,6 +113,7 @@ struct qcom_wled { u32 brightness; u32 sc_count; bool prev_state; + bool ovp_irq_disabled; }; static int qcom_wled_module_enable(struct qcom_wled *wled, int val) @@ -115,6 +123,28 @@ static int qcom_wled_module_enable(struct qcom_wled *wled, int val) rc = regmap_update_bits(wled->regmap, wled->ctrl_addr + QCOM_WLED_CTRL_MOD_ENABLE, QCOM_WLED_CTRL_MOD_EN_MASK, val << QCOM_WLED_CTRL_MODULE_EN_SHIFT); + if (rc < 0) + return rc; + /* + * Wait for at least 10ms before enabling OVP fault interrupt after + * enabling the module so that soft start is completed. Keep the OVP + * interrupt disabled when the module is disabled. + */ + if (val) { + usleep_range(QCOM_WLED_SOFT_START_DLY_US, + QCOM_WLED_SOFT_START_DLY_US + 1000); + + if (wled->cfg.ovp_irq > 0 && wled->ovp_irq_disabled) { + enable_irq(wled->cfg.ovp_irq); + wled->ovp_irq_disabled = false; + } + } else { + if (wled->cfg.ovp_irq > 0 && !wled->ovp_irq_disabled) { + disable_irq(wled->cfg.ovp_irq); + wled->ovp_irq_disabled = true; + } + } + return rc; } @@ -264,12 +294,42 @@ static irqreturn_t qcom_wled_sc_irq_handler(int irq, void *_wled) return IRQ_HANDLED; } +static irqreturn_t qcom_wled_ovp_irq_handler(int irq, void *_wled) +{ + struct qcom_wled *wled = _wled; + int rc; + u32 int_sts, fault_sts; + + rc = regmap_read(wled->regmap, + wled->ctrl_addr + QCOM_WLED_CTRL_INT_RT_STS, &int_sts); + if (rc < 0) { + pr_err("Error in reading WLED_INT_RT_STS rc=%d\n", rc); + return IRQ_HANDLED; + } + + rc = regmap_read(wled->regmap, wled->ctrl_addr + + QCOM_WLED_CTRL_FAULT_STATUS, &fault_sts); + if (rc < 0) { + pr_err("Error in reading WLED_FAULT_STATUS rc=%d\n", rc); + return IRQ_HANDLED; + } + + if (fault_sts & + (QCOM_WLED_CTRL_OVP_FAULT_BIT | QCOM_WLED_CTRL_ILIM_FAULT_BIT)) + pr_err("WLED OVP fault detected, int_sts=%x fault_sts= %x\n", + int_sts, fault_sts); + + return IRQ_HANDLED; +} + static int qcom_wled_setup(struct qcom_wled *wled) { int rc, temp, i; u8 sink_en = 0; + u32 val; u8 string_cfg = wled->cfg.string_cfg; int sc_irq = wled->cfg.sc_irq; + int ovp_irq = wled->cfg.ovp_irq; rc = regmap_update_bits(wled->regmap, wled->ctrl_addr + QCOM_WLED_CTRL_OVP, @@ -367,6 +427,25 @@ static int qcom_wled_setup(struct qcom_wled *wled) } } + if (ovp_irq >= 0) { + rc = devm_request_threaded_irq(&wled->pdev->dev, ovp_irq, + NULL, qcom_wled_ovp_irq_handler, IRQF_ONESHOT, + "qcom_wled_ovp_irq", wled); + if (rc < 0) { + dev_err(&wled->pdev->dev, "Unable to request ovp(%d) IRQ(err:%d)\n", + ovp_irq, rc); + return rc; + } + + rc = regmap_read(wled->regmap, wled->ctrl_addr + + QCOM_WLED_CTRL_MOD_ENABLE, &val); + /* disable the OVP irq only if the module is not enabled */ + if (!rc && !(val & QCOM_WLED_CTRL_MOD_EN_MASK)) { + disable_irq(ovp_irq); + wled->ovp_irq_disabled = true; + } + } + return 0; } @@ -539,6 +618,10 @@ static int qcom_wled_configure(struct qcom_wled *wled, struct device *dev) if (wled->cfg.sc_irq < 0) dev_dbg(&wled->pdev->dev, "sc irq is not used\n"); + wled->cfg.ovp_irq = platform_get_irq_byname(wled->pdev, "ovp-irq"); + if (wled->cfg.ovp_irq < 0) + dev_dbg(&wled->pdev->dev, "ovp irq is not used\n"); + return 0; }