From patchwork Mon Jun 12 10:23:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 774506 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wmTWS5LkGz9s65 for ; Mon, 12 Jun 2017 20:23:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752024AbdFLKXa (ORCPT ); Mon, 12 Jun 2017 06:23:30 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7082 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751599AbdFLKX3 (ORCPT ); Mon, 12 Jun 2017 06:23:29 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 12 Jun 2017 03:23:25 -0700 Received: from HQMAIL103.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 12 Jun 2017 03:23:28 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 12 Jun 2017 03:23:28 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Mon, 12 Jun 2017 10:23:28 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Mon, 12 Jun 2017 10:23:28 +0000 Received: from mperttunen-lnx.Nvidia.com (Not Verified[10.21.26.175]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Mon, 12 Jun 2017 03:23:28 -0700 From: Mikko Perttunen To: , CC: , , , , , Mikko Perttunen Subject: [PATCH v3 1/2] dt-bindings: Add bindings for nvidia, tegra186-ccplex-cluster Date: Mon, 12 Jun 2017 13:23:04 +0300 Message-ID: <1497262984-2346-1-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1496304245-24024-2-git-send-email-mperttunen@nvidia.com> References: <1496304245-24024-2-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen Acked-by: Rob Herring --- .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt new file mode 100644 index 000000000000..0c80cd8ee839 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt @@ -0,0 +1,20 @@ +NVIDIA Tegra CCPLEX_CLUSTER area + +The Tegra186 CCPLEX_CLUSTER area contains memory-mapped +registers that initiate CPU frequency/voltage transitions. + +Required properties: +- compatible: Should contain one of the following: + - "nvidia,tegra186-ccplex-cluster": for Tegra186 +- reg: Must contain an (offset, length) pair of the device's MMIO + register area +- nvidia,bpmp: phandle to BPMP device that can be queried for OPP tables + +Example: + + ccplex@e000000 { + compatible = "nvidia,tegra186-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x3fffff>, + + nvidia,bpmp = <&bpmp>; + };