From patchwork Thu Jun 1 08:04:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 769510 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wdfz34JTQz9sCX for ; Thu, 1 Jun 2017 18:05:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751290AbdFAIEm (ORCPT ); Thu, 1 Jun 2017 04:04:42 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11764 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751135AbdFAIEj (ORCPT ); Thu, 1 Jun 2017 04:04:39 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 01 Jun 2017 01:04:33 -0700 Received: from HQMAIL101.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 01 Jun 2017 01:04:38 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 01 Jun 2017 01:04:38 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Thu, 1 Jun 2017 08:04:38 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Thu, 1 Jun 2017 08:04:38 +0000 Received: from mperttunen-lnx.Nvidia.com (Not Verified[10.21.26.175]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Thu, 01 Jun 2017 01:04:38 -0700 From: Mikko Perttunen To: , , , CC: , , , Mikko Perttunen Subject: [PATCH v2 1/2] dt-bindings: Add bindings for nvidia, tegra186-ccplex-cluster Date: Thu, 1 Jun 2017 11:04:04 +0300 Message-ID: <1496304245-24024-2-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1496304245-24024-1-git-send-email-mperttunen@nvidia.com> References: <1496304245-24024-1-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen Acked-by: Rob Herring --- .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt new file mode 100644 index 000000000000..e8fb416c892b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt @@ -0,0 +1,17 @@ +NVIDIA Tegra CCPLEX_CLUSTER area + +Required properties: +- compatible: Should contain one of the following: + - "nvidia,tegra186-ccplex-cluster": for Tegra186 +- reg: Must contain an (offset, length) pair of the device's MMIO + register area +- nvidia,bpmp: phandle to BPMP device that can be queried for OPP tables + +Example: + + ccplex@e000000 { + compatible = "nvidia,tegra186-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x3fffff>, + + nvidia,bpmp = <&bpmp>; + };